From: Srinivas Ramana <sramana@codeaurora.org>
To: Nicolas Pitre <nicolas.pitre@linaro.org>
Cc: linux@armlinux.org.uk, will.deacon@arm.com,
linux-arm-msm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: Improper TTBCR for arm 32bit kernel decompression
Date: Sat, 10 Sep 2016 13:42:29 +0530 [thread overview]
Message-ID: <57D3C06D.4030908@codeaurora.org> (raw)
In-Reply-To: <alpine.LFD.2.20.1609091334120.14769@knanqh.ubzr>
On 09/09/2016 11:06 PM, Nicolas Pitre wrote:
> On Fri, 9 Sep 2016, Srinivas Ramana wrote:
>
>> Hello,
>>
>> While trying to boot arm-32 bit kernel, I came across a problem where TTBCR is
>> in improper state. If the bootloader uses the long descriptor format and jumps
>> to kernel decompressor code, TTBCR may not be in the right state. So, as soon
>> as the MMU is enabled, execution can not proceed further.
>>
>> Before enabling the MMU, it is required to clear the TTBCR.PD0 field to use
>> TTBR0 for translation table walks. Also, TTBCR.N should be reset to '0' to
>> indicate the correct base address width. The 'commit dbece45894d3a ("ARM:
>> 7501/1: decompressor: reset ttbcr for VMSA ARMv7 cores")' does the reset of
>> TTBCR.N, but doesn't consider all the bits for the size of TTBCR.N.
>>
>> when i tried the below change where i explicitly clear TTBCR.PD0 and use
>> correct mask for TTBCR.N, I see proper memory after MMU is enabled and
>> decompression succeeds.
>>
>> Request your comments on the change below. If it looks good, I can submit a
>> patch for inclusion.
>>
>> ---------------------8<----------------------------------
>> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
>> index af11c2f..5769f1f 100644
>> --- a/arch/arm/boot/compressed/head.S
>> +++ b/arch/arm/boot/compressed/head.S
>> @@ -779,7 +779,8 @@ __armv7_mmu_cache_on:
>> orrne r0, r0, #1 @ MMU enabled
>> movne r1, #0xfffffffd @ domain 0 = client
>> bic r6, r6, #1 << 31 @ 32-bit translation system
>> - bic r6, r6, #3 << 0 @ use only ttbr0
>> + bic r6, r6, #7 << 0 @ width of base address field
>> + bic r6, r6, #1 << 4 @ use only ttbr0
>
> You could combine those instructions like this:
>
> bic r6, r6, #(7 << 0) | (1 << 4) @ use only ttbr0
Sure, I can do that. Thanks for the suggestion. Will send out a patch
for review.
Thanks,
-- Srinivas R
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center,
Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative
Project.
WARNING: multiple messages have this Message-ID (diff)
From: sramana@codeaurora.org (Srinivas Ramana)
To: linux-arm-kernel@lists.infradead.org
Subject: Improper TTBCR for arm 32bit kernel decompression
Date: Sat, 10 Sep 2016 13:42:29 +0530 [thread overview]
Message-ID: <57D3C06D.4030908@codeaurora.org> (raw)
In-Reply-To: <alpine.LFD.2.20.1609091334120.14769@knanqh.ubzr>
On 09/09/2016 11:06 PM, Nicolas Pitre wrote:
> On Fri, 9 Sep 2016, Srinivas Ramana wrote:
>
>> Hello,
>>
>> While trying to boot arm-32 bit kernel, I came across a problem where TTBCR is
>> in improper state. If the bootloader uses the long descriptor format and jumps
>> to kernel decompressor code, TTBCR may not be in the right state. So, as soon
>> as the MMU is enabled, execution can not proceed further.
>>
>> Before enabling the MMU, it is required to clear the TTBCR.PD0 field to use
>> TTBR0 for translation table walks. Also, TTBCR.N should be reset to '0' to
>> indicate the correct base address width. The 'commit dbece45894d3a ("ARM:
>> 7501/1: decompressor: reset ttbcr for VMSA ARMv7 cores")' does the reset of
>> TTBCR.N, but doesn't consider all the bits for the size of TTBCR.N.
>>
>> when i tried the below change where i explicitly clear TTBCR.PD0 and use
>> correct mask for TTBCR.N, I see proper memory after MMU is enabled and
>> decompression succeeds.
>>
>> Request your comments on the change below. If it looks good, I can submit a
>> patch for inclusion.
>>
>> ---------------------8<----------------------------------
>> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
>> index af11c2f..5769f1f 100644
>> --- a/arch/arm/boot/compressed/head.S
>> +++ b/arch/arm/boot/compressed/head.S
>> @@ -779,7 +779,8 @@ __armv7_mmu_cache_on:
>> orrne r0, r0, #1 @ MMU enabled
>> movne r1, #0xfffffffd @ domain 0 = client
>> bic r6, r6, #1 << 31 @ 32-bit translation system
>> - bic r6, r6, #3 << 0 @ use only ttbr0
>> + bic r6, r6, #7 << 0 @ width of base address field
>> + bic r6, r6, #1 << 4 @ use only ttbr0
>
> You could combine those instructions like this:
>
> bic r6, r6, #(7 << 0) | (1 << 4) @ use only ttbr0
Sure, I can do that. Thanks for the suggestion. Will send out a patch
for review.
Thanks,
-- Srinivas R
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center,
Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative
Project.
next prev parent reply other threads:[~2016-09-10 8:12 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-09 16:34 Improper TTBCR for arm 32bit kernel decompression Srinivas Ramana
2016-09-09 16:34 ` Srinivas Ramana
2016-09-09 17:36 ` Nicolas Pitre
2016-09-09 17:36 ` Nicolas Pitre
2016-09-10 5:50 ` Srinivas Ramana
2016-09-10 5:50 ` Srinivas Ramana
2016-09-10 8:12 ` Srinivas Ramana [this message]
2016-09-10 8:12 ` Srinivas Ramana
2016-09-12 6:57 ` [PATCH] ARM: decompressor: reset ttbcr fields to use TTBR0 on ARMv7 Srinivas Ramana
2016-09-12 6:57 ` Srinivas Ramana
2016-09-12 10:23 ` Russell King - ARM Linux
2016-09-12 10:23 ` Russell King - ARM Linux
2016-09-12 17:51 ` Robin Murphy
2016-09-12 17:51 ` Robin Murphy
2016-09-13 14:52 ` Srinivas Ramana
2016-09-13 14:52 ` Srinivas Ramana
2016-09-27 12:16 ` Srinivas Ramana
2016-09-27 12:16 ` Srinivas Ramana
2016-09-27 12:54 ` Robin Murphy
2016-09-27 12:54 ` Robin Murphy
2016-09-28 12:45 ` [PATCH v1] " Srinivas Ramana
2016-09-28 12:45 ` Srinivas Ramana
2016-09-28 22:00 ` Russell King - ARM Linux
2016-09-28 22:00 ` Russell King - ARM Linux
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