From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mark yao Subject: Re: [PATCH 2/2] drm/vc4: Add support for interlaced modes on HDMI. Date: Thu, 29 Sep 2016 10:36:04 +0800 Message-ID: <57EC7E14.5050602@rock-chips.com> References: <20160929022045.24813-1-eric@anholt.net> <20160929022045.24813-2-eric@anholt.net> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.131]) by gabe.freedesktop.org (Postfix) with ESMTPS id 926046E075 for ; Thu, 29 Sep 2016 02:36:11 +0000 (UTC) In-Reply-To: <20160929022045.24813-2-eric@anholt.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Eric Anholt , dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org List-Id: dri-devel@lists.freedesktop.org T24gMjAxNuW5tDA55pyIMjnml6UgMTA6MjAsIEVyaWMgQW5ob2x0IHdyb3RlOgo+IFdlIGp1c3Qg bmVlZGVkIHRvIGluaXRpYWxpemUgYSBmZXcgbW9yZSBmaWVsZHMuCj4KPiBTaWduZWQtb2ZmLWJ5 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dApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0 b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754833AbcI2Cg1 (ORCPT ); Wed, 28 Sep 2016 22:36:27 -0400 Received: from regular1.263xmail.com ([211.150.99.131]:48057 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753068AbcI2CgT (ORCPT ); Wed, 28 Sep 2016 22:36:19 -0400 X-263anti-spam: KSV:0;BIG:0;ABS:1;DNS:0;ATT:0;SPF:S; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 1 X-SKE-CHECKED: 1 X-ADDR-CHECKED4: 1 X-RL-SENDER: mark.yao@rock-chips.com X-FST-TO: linux-kernel@vger.kernel.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: mark.yao@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH 2/2] drm/vc4: Add support for interlaced modes on HDMI. To: Eric Anholt , dri-devel@lists.freedesktop.org References: <20160929022045.24813-1-eric@anholt.net> <20160929022045.24813-2-eric@anholt.net> Cc: linux-kernel@vger.kernel.org From: Mark yao Message-ID: <57EC7E14.5050602@rock-chips.com> Date: Thu, 29 Sep 2016 10:36:04 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <20160929022045.24813-2-eric@anholt.net> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2016年09月29日 10:20, Eric Anholt wrote: > We just needed to initialize a few more fields. > > Signed-off-by: Eric Anholt > --- > drivers/gpu/drm/vc4/vc4_crtc.c | 17 ++++++++++++++--- > drivers/gpu/drm/vc4/vc4_hdmi.c | 12 ++++++++---- > drivers/gpu/drm/vc4/vc4_regs.h | 3 +++ > 3 files changed, 25 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c > index 8fc2b731b59a..d575f8aa3273 100644 > --- a/drivers/gpu/drm/vc4/vc4_crtc.c > +++ b/drivers/gpu/drm/vc4/vc4_crtc.c > @@ -428,13 +428,24 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) > VC4_SET_FIELD(mode->vsync_start - mode->vdisplay, > PV_VERTB_VFP) | > VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE)); > + > + /* We set up first field even mode for HDMI. VEC's > + * NTSC mode would want first field odd instead, once > + * we support it (to do so, set ODD_FIRST and put the > + * delay in VSYNCD_EVEN instead). > + */ > + CRTC_WRITE(PV_V_CONTROL, > + PV_VCONTROL_CONTINUOUS | > + PV_VCONTROL_INTERLACE | > + VC4_SET_FIELD(mode->htotal / 2, > + PV_VCONTROL_ODD_DELAY)); > + CRTC_WRITE(PV_VSYNCD_EVEN, 0); > + } else { > + CRTC_WRITE(PV_V_CONTROL, PV_VCONTROL_CONTINUOUS); > } > > CRTC_WRITE(PV_HACT_ACT, mode->hdisplay); > > - CRTC_WRITE(PV_V_CONTROL, > - PV_VCONTROL_CONTINUOUS | > - (interlace ? PV_VCONTROL_INTERLACE : 0)); > > CRTC_WRITE(PV_CONTROL, > VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | > diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c > index 5770d6704f4b..6095e48fcf46 100644 > --- a/drivers/gpu/drm/vc4/vc4_hdmi.c > +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c > @@ -246,7 +246,7 @@ static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev, > connector->polled = (DRM_CONNECTOR_POLL_CONNECT | > DRM_CONNECTOR_POLL_DISCONNECT); > > - connector->interlace_allowed = 0; > + connector->interlace_allowed = true; > connector->doublescan_allowed = 0; > > drm_mode_connector_attach_encoder(connector, encoder); > @@ -278,8 +278,8 @@ static void vc4_hdmi_encoder_mode_set(struct drm_encoder *encoder, > bool debug_dump_regs = false; > bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; > bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; > - u32 vactive = (mode->vdisplay >> > - ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0)); > + bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; > + u32 vactive = mode->vdisplay >> interlaced; How about use mode->crtc_vdisplay: see this: drm_mode_set_crtcinfo() if (p->flags & DRM_MODE_FLAG_INTERLACE) { if (adjust_flags & CRTC_INTERLACE_HALVE_V) { p->crtc_vdisplay /= 2; p->crtc_vsync_start /= 2; p->crtc_vsync_end /= 2; p->crtc_vtotal /= 2; } } Thanks > u32 verta = (VC4_SET_FIELD(mode->vsync_end - mode->vsync_start, > VC4_HDMI_VERTA_VSP) | > VC4_SET_FIELD(mode->vsync_start - mode->vdisplay, > @@ -288,6 +288,10 @@ static void vc4_hdmi_encoder_mode_set(struct drm_encoder *encoder, > u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | > VC4_SET_FIELD(mode->vtotal - mode->vsync_end, > VC4_HDMI_VERTB_VBP)); > + u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | > + VC4_SET_FIELD(mode->vtotal - mode->vsync_end - > + interlaced, > + VC4_HDMI_VERTB_VBP)); > > if (debug_dump_regs) { > DRM_INFO("HDMI regs before:\n"); > @@ -319,7 +323,7 @@ static void vc4_hdmi_encoder_mode_set(struct drm_encoder *encoder, > HDMI_WRITE(VC4_HDMI_VERTA0, verta); > HDMI_WRITE(VC4_HDMI_VERTA1, verta); > > - HDMI_WRITE(VC4_HDMI_VERTB0, vertb); > + HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even); > HDMI_WRITE(VC4_HDMI_VERTB1, vertb); > > HD_WRITE(VC4_HD_VID_CTL, > diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h > index 160942a9180e..fec7b5ef058b 100644 > --- a/drivers/gpu/drm/vc4/vc4_regs.h > +++ b/drivers/gpu/drm/vc4/vc4_regs.h > @@ -183,6 +183,9 @@ > # define PV_CONTROL_EN BIT(0) > > #define PV_V_CONTROL 0x04 > +# define PV_VCONTROL_ODD_DELAY_MASK VC4_MASK(22, 6) > +# define PV_VCONTROL_ODD_DELAY_SHIFT 6 > +# define PV_VCONTROL_ODD_FIRST BIT(5) > # define PV_VCONTROL_INTERLACE BIT(4) > # define PV_VCONTROL_CONTINUOUS BIT(1) > # define PV_VCONTROL_VIDEN BIT(0) -- Ｍark Yao