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Thu, 27 Apr 2023 19:09:55 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9DAF8C433EF; Thu, 27 Apr 2023 19:09:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1682622594; bh=4MuGyWTQQD8YDc9ZDP5EuTvCXfhs1RGXEGefTe8GbFs=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=OEyoAdAg2oHj1kpUaFAUQnORGNgUcMTwXna94WirWc4/7OFURAmKcVKLlVxGAFkME toxsg2t0o0U7Q+9nKKAWfOe1B/t1z3g1kRabot2L3KU7VvngL293h0JsGHTQ534ZJP wb/t5pQP0ryuyOaWJAQ0Akswuclq647TVGmt1KHHbj8adW21pY6mXqBy4ogxoG3XiT nl8v4DuX6FhDVh3IAmmeTltphT6HmwSaAdaxUAAee3iYvoH2HR36H28EF1sUk2sy35 kac9ZjDMYlfFNHS8ZZYJ4TPcDUlbU3BEvZYy9X6SsaJklf3YKOr0nvFwrR0eNy/XBZ ccVK16xunjKbA== Message-ID: <57dd81d0-510e-0fab-670d-1109eb8dd974@kernel.org> Date: Thu, 27 Apr 2023 14:09:48 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v3 29/65] clk: socfpga: gate: Add a determine_rate hook Content-Language: en-US To: Maxime Ripard References: <20221018-clk-range-checks-fixes-v3-0-9a1358472d52@cerno.tech> <20221018-clk-range-checks-fixes-v3-29-9a1358472d52@cerno.tech> <679921ee-98d4-d6ef-5934-e009fd4b31fc@kernel.org> From: Dinh Nguyen In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-MailFrom: dinguyen@kernel.org X-Mailman-Rule-Hits: nonmember-moderation X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1 Message-ID-Hash: 2LLU2JS3YLP3QU7CORJEXDTOQFEYXOHS X-Message-ID-Hash: 2LLU2JS3YLP3QU7CORJEXDTOQFEYXOHS X-Mailman-Approved-At: Mon, 01 May 2023 06:41:14 +0000 CC: Michael Turquette , Stephen Boyd , =?UTF-8?Q?Andreas_F=c3=a4rber?= , Manivannan Sadhasivam , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea , Max Filippov , Charles Keepax , Richard Fitzgerald , Maxime Coquelin , Alexandre Torgue , Luca Ceresoli , David Lechner , Sekhar Nori , Abel Vesa , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Matthias Brugger , Geert Uytterhoeven , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Ulf Hansson , Linus Walleij , David Airlie , Daniel Vetter , Vinod Koul , Kishon Vijay Abraham I , Alessandro Zummo , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Liam Girdwood , Mark Brown , Takashi Iwai , Paul Cercueil , Orson Zhai , Baolin Wang , Chunyan Zhang , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, patches@opensource.cirrus.com, linux-stm32@st-md-mailman.stormreply.com, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-phy@lists.infradead.org, linux-rtc@vger.kernel.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org, linux-mips@vger.kernel.org X-Mailman-Version: 3.3.8 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Hi Maxime, On 4/25/23 09:48, Maxime Ripard wrote: > Hi Dinh, > > On Mon, Apr 24, 2023 at 01:32:28PM -0500, Dinh Nguyen wrote: >> On 4/4/23 05:11, Maxime Ripard wrote: >>> The SoCFGPA gate clock implements a mux with a set_parent hook, but >>> doesn't provide a determine_rate implementation. >>> >>> This is a bit odd, since set_parent() is there to, as its name implies, >>> change the parent of a clock. However, the most likely candidate to >>> trigger that parent change is a call to clk_set_rate(), with >>> determine_rate() figuring out which parent is the best suited for a >>> given rate. >>> >>> The other trigger would be a call to clk_set_parent(), but it's far less >>> used, and it doesn't look like there's any obvious user for that clock. >>> >>> So, the set_parent hook is effectively unused, possibly because of an >>> oversight. However, it could also be an explicit decision by the >>> original author to avoid any reparenting but through an explicit call to >>> clk_set_parent(). >>> >>> The latter case would be equivalent to setting the flag >>> CLK_SET_RATE_NO_REPARENT, together with setting our determine_rate hook >>> to __clk_mux_determine_rate(). Indeed, if no determine_rate >>> implementation is provided, clk_round_rate() (through >>> clk_core_round_rate_nolock()) will call itself on the parent if >>> CLK_SET_RATE_PARENT is set, and will not change the clock rate >>> otherwise. __clk_mux_determine_rate() has the exact same behavior when >>> CLK_SET_RATE_NO_REPARENT is set. >>> >>> And if it was an oversight, then we are at least explicit about our >>> behavior now and it can be further refined down the line. >>> >>> Signed-off-by: Maxime Ripard >>> --- >>> drivers/clk/socfpga/clk-gate.c | 3 ++- >>> 1 file changed, 2 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c >>> index 32ccda960f28..cbba8462a09e 100644 >>> --- a/drivers/clk/socfpga/clk-gate.c >>> +++ b/drivers/clk/socfpga/clk-gate.c >>> @@ -110,6 +110,7 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk, >>> static struct clk_ops gateclk_ops = { >>> .recalc_rate = socfpga_clk_recalc_rate, >>> + .determine_rate = __clk_mux_determine_rate, >>> .get_parent = socfpga_clk_get_parent, >>> .set_parent = socfpga_clk_set_parent, >>> }; >>> @@ -166,7 +167,7 @@ void __init socfpga_gate_init(struct device_node *node) >>> init.name = clk_name; >>> init.ops = ops; >>> - init.flags = 0; >>> + init.flags = CLK_SET_RATE_NO_REPARENT; >>> init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS); >>> if (init.num_parents < 2) { >>> >> >> This patch broke SoCFPGA boot serial port. The characters are mangled. > > Do you have any other access to that board? If so, could you dump > clk_summary in debugfs with and without that patch? > That dump from the clk_summary are identical for both cases. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60F3FC77B7E for ; Thu, 27 Apr 2023 19:09:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244381AbjD0TJ6 (ORCPT ); Thu, 27 Apr 2023 15:09:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244687AbjD0TJ5 (ORCPT ); Thu, 27 Apr 2023 15:09:57 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D01E79E; Thu, 27 Apr 2023 12:09:55 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 6BE9D63F22; Thu, 27 Apr 2023 19:09:55 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9DAF8C433EF; Thu, 27 Apr 2023 19:09:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1682622594; bh=4MuGyWTQQD8YDc9ZDP5EuTvCXfhs1RGXEGefTe8GbFs=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=OEyoAdAg2oHj1kpUaFAUQnORGNgUcMTwXna94WirWc4/7OFURAmKcVKLlVxGAFkME toxsg2t0o0U7Q+9nKKAWfOe1B/t1z3g1kRabot2L3KU7VvngL293h0JsGHTQ534ZJP wb/t5pQP0ryuyOaWJAQ0Akswuclq647TVGmt1KHHbj8adW21pY6mXqBy4ogxoG3XiT nl8v4DuX6FhDVh3IAmmeTltphT6HmwSaAdaxUAAee3iYvoH2HR36H28EF1sUk2sy35 kac9ZjDMYlfFNHS8ZZYJ4TPcDUlbU3BEvZYy9X6SsaJklf3YKOr0nvFwrR0eNy/XBZ ccVK16xunjKbA== Message-ID: <57dd81d0-510e-0fab-670d-1109eb8dd974@kernel.org> Date: Thu, 27 Apr 2023 14:09:48 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v3 29/65] clk: socfpga: gate: Add a determine_rate hook Content-Language: en-US To: Maxime Ripard Cc: Michael Turquette , Stephen Boyd , =?UTF-8?Q?Andreas_F=c3=a4rber?= , Manivannan Sadhasivam , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea , Max Filippov , Charles Keepax , Richard Fitzgerald , Maxime Coquelin , Alexandre Torgue , Luca Ceresoli , David Lechner , Sekhar Nori , Abel Vesa , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Matthias Brugger , Geert Uytterhoeven , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Ulf Hansson , Linus Walleij , David Airlie , Daniel Vetter , Vinod Koul , Kishon Vijay Abraham I , Alessandro Zummo , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Paul Cercueil , Orson Zhai , Baolin Wang , Chunyan Zhang , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, patches@opensource.cirrus.com, linux-stm32@st-md-mailman.stormreply.com, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-phy@lists.infradead.org, linux-rtc@vger.kernel.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org, linux-mips@vger.kernel.org References: <20221018-clk-range-checks-fixes-v3-0-9a1358472d52@cerno.tech> <20221018-clk-range-checks-fixes-v3-29-9a1358472d52@cerno.tech> <679921ee-98d4-d6ef-5934-e009fd4b31fc@kernel.org> From: Dinh Nguyen In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Hi Maxime, On 4/25/23 09:48, Maxime Ripard wrote: > Hi Dinh, > > On Mon, Apr 24, 2023 at 01:32:28PM -0500, Dinh Nguyen wrote: >> On 4/4/23 05:11, Maxime Ripard wrote: >>> The SoCFGPA gate clock implements a mux with a set_parent hook, but >>> doesn't provide a determine_rate implementation. >>> >>> This is a bit odd, since set_parent() is there to, as its name implies, >>> change the parent of a clock. However, the most likely candidate to >>> trigger that parent change is a call to clk_set_rate(), with >>> determine_rate() figuring out which parent is the best suited for a >>> given rate. >>> >>> The other trigger would be a call to clk_set_parent(), but it's far less >>> used, and it doesn't look like there's any obvious user for that clock. >>> >>> So, the set_parent hook is effectively unused, possibly because of an >>> oversight. However, it could also be an explicit decision by the >>> original author to avoid any reparenting but through an explicit call to >>> clk_set_parent(). >>> >>> The latter case would be equivalent to setting the flag >>> CLK_SET_RATE_NO_REPARENT, together with setting our determine_rate hook >>> to __clk_mux_determine_rate(). Indeed, if no determine_rate >>> implementation is provided, clk_round_rate() (through >>> clk_core_round_rate_nolock()) will call itself on the parent if >>> CLK_SET_RATE_PARENT is set, and will not change the clock rate >>> otherwise. __clk_mux_determine_rate() has the exact same behavior when >>> CLK_SET_RATE_NO_REPARENT is set. >>> >>> And if it was an oversight, then we are at least explicit about our >>> behavior now and it can be further refined down the line. >>> >>> Signed-off-by: Maxime Ripard >>> --- >>> drivers/clk/socfpga/clk-gate.c | 3 ++- >>> 1 file changed, 2 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c >>> index 32ccda960f28..cbba8462a09e 100644 >>> --- a/drivers/clk/socfpga/clk-gate.c >>> +++ b/drivers/clk/socfpga/clk-gate.c >>> @@ -110,6 +110,7 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk, >>> static struct clk_ops gateclk_ops = { >>> .recalc_rate = socfpga_clk_recalc_rate, >>> + .determine_rate = __clk_mux_determine_rate, >>> .get_parent = socfpga_clk_get_parent, >>> .set_parent = socfpga_clk_set_parent, >>> }; >>> @@ -166,7 +167,7 @@ void __init socfpga_gate_init(struct device_node *node) >>> init.name = clk_name; >>> init.ops = ops; >>> - init.flags = 0; >>> + init.flags = CLK_SET_RATE_NO_REPARENT; >>> init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS); >>> if (init.num_parents < 2) { >>> >> >> This patch broke SoCFPGA boot serial port. The characters are mangled. > > Do you have any other access to that board? If so, could you dump > clk_summary in debugfs with and without that patch? > That dump from the clk_summary are identical for both cases. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 55F24C7EE29 for ; Thu, 27 Apr 2023 19:10:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=wHWqAAl1XXGG4NW+Ae9n2nqGmwMyZ5WEWF3pJG9YlNw=; b=cLIkIb5Q3MTfxF eU+2KaC+aGHTPQ+wNyTkwZkWTGVNdXxvayRhMv9dKq2ShIK+9vSSXiqgVKjTaARlMTvDHVg9zscRY k1lJVhtrsU6fIAp7f+FBrAjfof0oI/Gl/bP852VdFFOFi1ikox3E4J8TuYp3tOGotPJOMMmn1RXSG VxEwwailcLMhsEc+wyl7fH623RN6LrR6PWKis8HCFVrdhMibuDZSYlHgjo9iAR00v2/J9/1xE5DaD ft37U9xrXHmQpcAk6aEoJqo2rT5lK5U9HoOghB2sQ/VBN0G5KfOO76my3Mk62cvqp397UgUAeNDpl JmB1qJ5SNsjCVwlPAK1w==; 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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v3 29/65] clk: socfpga: gate: Add a determine_rate hook Content-Language: en-US To: Maxime Ripard Cc: Michael Turquette , Stephen Boyd , =?UTF-8?Q?Andreas_F=c3=a4rber?= , Manivannan Sadhasivam , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea , Max Filippov , Charles Keepax , Richard Fitzgerald , Maxime Coquelin , Alexandre Torgue , Luca Ceresoli , David Lechner , Sekhar Nori , Abel Vesa , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Matthias Brugger , Geert Uytterhoeven , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Ulf Hansson , Linus Walleij , David Airlie , Daniel Vetter , Vinod Koul , Kishon Vijay Abraham I , Alessandro Zummo , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Paul Cercueil , Orson Zhai , Baolin Wang , Chunyan Zhang , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, patches@opensource.cirrus.com, linux-stm32@st-md-mailman.stormreply.com, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-phy@lists.infradead.org, linux-rtc@vger.kernel.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org, linux-mips@vger.kernel.org References: <20221018-clk-range-checks-fixes-v3-0-9a1358472d52@cerno.tech> <20221018-clk-range-checks-fixes-v3-29-9a1358472d52@cerno.tech> <679921ee-98d4-d6ef-5934-e009fd4b31fc@kernel.org> From: Dinh Nguyen In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230427_120956_707835_9E04FC37 X-CRM114-Status: GOOD ( 26.15 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Hi Maxime, On 4/25/23 09:48, Maxime Ripard wrote: > Hi Dinh, > > On Mon, Apr 24, 2023 at 01:32:28PM -0500, Dinh Nguyen wrote: >> On 4/4/23 05:11, Maxime Ripard wrote: >>> The SoCFGPA gate clock implements a mux with a set_parent hook, but >>> doesn't provide a determine_rate implementation. >>> >>> This is a bit odd, since set_parent() is there to, as its name implies, >>> change the parent of a clock. However, the most likely candidate to >>> trigger that parent change is a call to clk_set_rate(), with >>> determine_rate() figuring out which parent is the best suited for a >>> given rate. >>> >>> The other trigger would be a call to clk_set_parent(), but it's far less >>> used, and it doesn't look like there's any obvious user for that clock. >>> >>> So, the set_parent hook is effectively unused, possibly because of an >>> oversight. However, it could also be an explicit decision by the >>> original author to avoid any reparenting but through an explicit call to >>> clk_set_parent(). >>> >>> The latter case would be equivalent to setting the flag >>> CLK_SET_RATE_NO_REPARENT, together with setting our determine_rate hook >>> to __clk_mux_determine_rate(). Indeed, if no determine_rate >>> implementation is provided, clk_round_rate() (through >>> clk_core_round_rate_nolock()) will call itself on the parent if >>> CLK_SET_RATE_PARENT is set, and will not change the clock rate >>> otherwise. __clk_mux_determine_rate() has the exact same behavior when >>> CLK_SET_RATE_NO_REPARENT is set. >>> >>> And if it was an oversight, then we are at least explicit about our >>> behavior now and it can be further refined down the line. >>> >>> Signed-off-by: Maxime Ripard >>> --- >>> drivers/clk/socfpga/clk-gate.c | 3 ++- >>> 1 file changed, 2 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c >>> index 32ccda960f28..cbba8462a09e 100644 >>> --- a/drivers/clk/socfpga/clk-gate.c >>> +++ b/drivers/clk/socfpga/clk-gate.c >>> @@ -110,6 +110,7 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk, >>> static struct clk_ops gateclk_ops = { >>> .recalc_rate = socfpga_clk_recalc_rate, >>> + .determine_rate = __clk_mux_determine_rate, >>> .get_parent = socfpga_clk_get_parent, >>> .set_parent = socfpga_clk_set_parent, >>> }; >>> @@ -166,7 +167,7 @@ void __init socfpga_gate_init(struct device_node *node) >>> init.name = clk_name; >>> init.ops = ops; >>> - init.flags = 0; >>> + init.flags = CLK_SET_RATE_NO_REPARENT; >>> init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS); >>> if (init.num_parents < 2) { >>> >> >> This patch broke SoCFPGA boot serial port. The characters are mangled. > > Do you have any other access to that board? If so, could you dump > clk_summary in debugfs with and without that patch? > That dump from the clk_summary are identical for both cases. -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A654FC77B73 for ; Thu, 27 Apr 2023 19:09:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AB5E810E109; Thu, 27 Apr 2023 19:09:57 +0000 (UTC) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by gabe.freedesktop.org (Postfix) with ESMTPS id B823810E109 for ; Thu, 27 Apr 2023 19:09:56 +0000 (UTC) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 65910637E8; Thu, 27 Apr 2023 19:09:55 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9DAF8C433EF; Thu, 27 Apr 2023 19:09:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1682622594; bh=4MuGyWTQQD8YDc9ZDP5EuTvCXfhs1RGXEGefTe8GbFs=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=OEyoAdAg2oHj1kpUaFAUQnORGNgUcMTwXna94WirWc4/7OFURAmKcVKLlVxGAFkME toxsg2t0o0U7Q+9nKKAWfOe1B/t1z3g1kRabot2L3KU7VvngL293h0JsGHTQ534ZJP wb/t5pQP0ryuyOaWJAQ0Akswuclq647TVGmt1KHHbj8adW21pY6mXqBy4ogxoG3XiT nl8v4DuX6FhDVh3IAmmeTltphT6HmwSaAdaxUAAee3iYvoH2HR36H28EF1sUk2sy35 kac9ZjDMYlfFNHS8ZZYJ4TPcDUlbU3BEvZYy9X6SsaJklf3YKOr0nvFwrR0eNy/XBZ ccVK16xunjKbA== Message-ID: <57dd81d0-510e-0fab-670d-1109eb8dd974@kernel.org> Date: Thu, 27 Apr 2023 14:09:48 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v3 29/65] clk: socfpga: gate: Add a determine_rate hook Content-Language: en-US To: Maxime Ripard References: <20221018-clk-range-checks-fixes-v3-0-9a1358472d52@cerno.tech> <20221018-clk-range-checks-fixes-v3-29-9a1358472d52@cerno.tech> <679921ee-98d4-d6ef-5934-e009fd4b31fc@kernel.org> From: Dinh Nguyen In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexandre Belloni , Prashant Gaikwad , Geert Uytterhoeven , Michael Turquette , Sekhar Nori , Alexandre Torgue , dri-devel@lists.freedesktop.org, Liam Girdwood , Paul Cercueil , Max Filippov , Thierry Reding , linux-phy@lists.infradead.org, linux-clk@vger.kernel.org, Abel Vesa , Kishon Vijay Abraham I , Samuel Holland , Takashi Iwai , linux-tegra@vger.kernel.org, Jernej Skrabec , Jonathan Hunter , Chen-Yu Tsai , NXP Linux Team , Orson Zhai , Ulf Hansson , linux-mips@vger.kernel.org, Luca Ceresoli , linux-rtc@vger.kernel.org, Charles Keepax , David Lechner , alsa-devel@alsa-project.org, Manivannan Sadhasivam , linux-kernel@vger.kernel.org, Sascha Hauer , linux-actions@lists.infradead.org, Richard Fitzgerald , Mark Brown , linux-mediatek@lists.infradead.org, Baolin Wang , Matthias Brugger , Jaroslav Kysela , linux-arm-kernel@lists.infradead.org, AngeloGioacchino Del Regno , Alessandro Zummo , Maxime Coquelin , Stephen Boyd , patches@opensource.cirrus.com, Peter De Schrijver , linux-stm32@st-md-mailman.stormreply.com, Nicolas Ferre , =?UTF-8?Q?Andreas_F=c3=a4rber?= , linux-renesas-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, Vinod Koul , Pengutronix Kernel Team , Chunyan Zhang , Shawn Guo , Claudiu Beznea Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Maxime, On 4/25/23 09:48, Maxime Ripard wrote: > Hi Dinh, > > On Mon, Apr 24, 2023 at 01:32:28PM -0500, Dinh Nguyen wrote: >> On 4/4/23 05:11, Maxime Ripard wrote: >>> The SoCFGPA gate clock implements a mux with a set_parent hook, but >>> doesn't provide a determine_rate implementation. >>> >>> This is a bit odd, since set_parent() is there to, as its name implies, >>> change the parent of a clock. However, the most likely candidate to >>> trigger that parent change is a call to clk_set_rate(), with >>> determine_rate() figuring out which parent is the best suited for a >>> given rate. >>> >>> The other trigger would be a call to clk_set_parent(), but it's far less >>> used, and it doesn't look like there's any obvious user for that clock. >>> >>> So, the set_parent hook is effectively unused, possibly because of an >>> oversight. However, it could also be an explicit decision by the >>> original author to avoid any reparenting but through an explicit call to >>> clk_set_parent(). >>> >>> The latter case would be equivalent to setting the flag >>> CLK_SET_RATE_NO_REPARENT, together with setting our determine_rate hook >>> to __clk_mux_determine_rate(). Indeed, if no determine_rate >>> implementation is provided, clk_round_rate() (through >>> clk_core_round_rate_nolock()) will call itself on the parent if >>> CLK_SET_RATE_PARENT is set, and will not change the clock rate >>> otherwise. __clk_mux_determine_rate() has the exact same behavior when >>> CLK_SET_RATE_NO_REPARENT is set. >>> >>> And if it was an oversight, then we are at least explicit about our >>> behavior now and it can be further refined down the line. >>> >>> Signed-off-by: Maxime Ripard >>> --- >>> drivers/clk/socfpga/clk-gate.c | 3 ++- >>> 1 file changed, 2 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c >>> index 32ccda960f28..cbba8462a09e 100644 >>> --- a/drivers/clk/socfpga/clk-gate.c >>> +++ b/drivers/clk/socfpga/clk-gate.c >>> @@ -110,6 +110,7 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk, >>> static struct clk_ops gateclk_ops = { >>> .recalc_rate = socfpga_clk_recalc_rate, >>> + .determine_rate = __clk_mux_determine_rate, >>> .get_parent = socfpga_clk_get_parent, >>> .set_parent = socfpga_clk_set_parent, >>> }; >>> @@ -166,7 +167,7 @@ void __init socfpga_gate_init(struct device_node *node) >>> init.name = clk_name; >>> init.ops = ops; >>> - init.flags = 0; >>> + init.flags = CLK_SET_RATE_NO_REPARENT; >>> init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS); >>> if (init.num_parents < 2) { >>> >> >> This patch broke SoCFPGA boot serial port. The characters are mangled. > > Do you have any other access to that board? If so, could you dump > clk_summary in debugfs with and without that patch? > That dump from the clk_summary are identical for both cases.