From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andy Furniss Subject: Re: [PATCH] drm/amdgpu: set bypass mode when uvd is idle. Date: Sun, 6 Nov 2016 20:30:59 +0000 Message-ID: <581F9303.80403@gmail.com> References: <1478160844-19257-1-git-send-email-Rex.Zhu@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: "Zhu, Rex" , "Deucher, Alexander" , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" Wmh1LCBSZXggd3JvdGU6Cj4+Pj4gSXMgdGhlcmUgYW55IGhhcm0gaW4ganVzdCBhbHdheXMgcHV0 dGluZyBpdCBpbnRvIGJ5cGFzcyBtb2RlIG9yCj4+Pj4gZG9lcyBpdCBpbnRlcmFjdCBiYWRseSB3 aXRoIFBHPyAgUHJlc3VtYWJseSBpdCBkb2VzIChvdGhlcndpc2UKPj4+PiB3ZSB3b3VsZG4ndCBu ZWVkIHRoaXMgcGF0Y2gpLCBpdCB3b3VsZCBiZSBnb29kIHRvIG5vdGUgd2h5Lgo+Cj4gUmV4OiB3 aGVuIFVWRCBQRyBlbmFibGVkLCBEQ0xLL1ZDTEsgd2lsbCBiZSB0dXJuIG9mZiB3aGVuIHV2ZCBp cwo+IGlkbGUoRENMSz1PRkYpLiBJZiB3ZSBzZXQgYnlwYXNzIG1vZGU9MSwgZGNsay92Y2xrIHdp bGwgYmUgYnlwYXNzZWQKPiB0byBhbiBleHRlcm5hbCDigJhCeXBhc3PigJkgY2xvY2soRENMSyA9 IDEwME1IeikKPgo+IFNvIGl0IGlzIHVubmVjZXNzYXJ5IHRvIHNldCBieXBhc3MgbW9kZSB3aGVu IFBHIGVuYWJsZWQuCj4KPiArdXZkX3Y1XzBfc2V0X2J5cGFzc19tb2RlKGFkZXYsICFlbmFibGUp OyBUaGlzIGNoYW5nZSBpcyBiZWNhdXNlCj4gdG9tJ3MgY29tbWl0IDcyY2I2NGMxZjZhM2E4MTI5 YWYzNDFlOTA0MThhNjg3YzQ5NzFhNDAgRml4IHRoZQo+IHNlcXVlbmNlIG9mIFVWRCBwb3dlcmdh dGUgZnVuY3Rpb24gaW4gc211N19jbG9ja2dhdGluZy5jLgoKSSB3YXMgYWJvdXQgdG8gZmlsZSBh IGJ1ZyB0aWxsIEkgdHJpZWQgdGhpcyB3aGljaCBmaXhlcyBVVkQgcGVyZgpvbiBteSBSOTI4NSAr IGFnZDVmIGRybS1uZXh0LTQuMTAtd2lwLgoKQWRkaXRpb25hbCB1bnJlbGF0ZWQgcXVlc3Rpb24g PSBJIG5vdGljZSB0aGF0IFVWRCBkb2VzIG5vdCBzZWVtCnRvIHNldCBvdGhlciBjbG9ja3MgcXVp dGUgaGlnaCBlbm91Z2ggd2hlbiB1c2VkLgoKRm9yIHBsYXliYWNrIHRoZSB2byBtYXkgYnVtcCB0 aGluZ3MgdXAgYSBiaXQsIGJ1dCBldmVuIHRoZW4gaXQgY2FuIGJlIGEgYml0CmJvcmRlcmxpbmUg Zm9yIHBsYXlpbmcgaGlnaCBiaXRyYXRlIFVIRCB3aXRoIHBvd2VycGxheSBvbiBhdXRvLgoKUHVy ZSBkZWNvZGUgYmVuY2htYXJrcyBsaWtlCgpmZm1wZWcgLWh3YWNjZWwgdmRwYXUgLWkgaGlnaC1i aXRyYXRlLTIxNjBwNjAtdmlkIC1waXhfZm10IG52MTIgLWYgbnVsbCAtCgpnbyBmcm9tIDYzIC0+ IDgxIGZwcywgcG93ZXJwbGF5IGF1dG8gLT4gaGlnaC4KX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX18KYW1kLWdmeCBtYWlsaW5nIGxpc3QKYW1kLWdmeEBsaXN0 cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9s aXN0aW5mby9hbWQtZ2Z4Cg==