diff for duplicates of <582B3546.8040404@hisilicon.com> diff --git a/a/1.txt b/N1/1.txt index 701b8a7..0d5488e 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -63,7 +63,7 @@ Wei > + compatible = "hisilicon,hip07-d05"; > + > + /* the mem node will be updated by UEFI. */ -> + memory at 0 { +> + memory@0 { > + device_type = "memory"; > + reg = <0x0 0x00000000 0x0 0x40000000>; > + numa-node-id = <0>; @@ -385,7 +385,7 @@ Wei > + }; > + }; > + -> + cpu0: cpu at 10000 { +> + cpu0: cpu@10000 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x10000>; @@ -394,7 +394,7 @@ Wei > + numa-node-id = <0>; > + }; > + -> + cpu1: cpu at 10001 { +> + cpu1: cpu@10001 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x10001>; @@ -403,7 +403,7 @@ Wei > + numa-node-id = <0>; > + }; > + -> + cpu2: cpu at 10002 { +> + cpu2: cpu@10002 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x10002>; @@ -412,7 +412,7 @@ Wei > + numa-node-id = <0>; > + }; > + -> + cpu3: cpu at 10003 { +> + cpu3: cpu@10003 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x10003>; @@ -421,7 +421,7 @@ Wei > + numa-node-id = <0>; > + }; > + -> + cpu4: cpu at 10100 { +> + cpu4: cpu@10100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x10100>; @@ -430,7 +430,7 @@ Wei > + numa-node-id = <0>; > + }; > + -> + cpu5: cpu at 10101 { +> + cpu5: cpu@10101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x10101>; @@ -439,7 +439,7 @@ Wei > + numa-node-id = <0>; > + }; > + -> + cpu6: cpu at 10102 { +> + cpu6: cpu@10102 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x10102>; @@ -448,7 +448,7 @@ Wei > + numa-node-id = <0>; > + }; > + -> + cpu7: cpu at 10103 { +> + cpu7: cpu@10103 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x10103>; @@ -457,7 +457,7 @@ Wei > + numa-node-id = <0>; > + }; > + -> + cpu8: cpu at 10200 { +> + cpu8: cpu@10200 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x10200>; @@ -466,7 +466,7 @@ Wei > + numa-node-id = <0>; > + }; > + -> + cpu9: cpu at 10201 { +> + cpu9: cpu@10201 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x10201>; @@ -475,7 +475,7 @@ Wei > + numa-node-id = <0>; > + }; > + -> + cpu10: cpu at 10202 { +> + cpu10: cpu@10202 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x10202>; @@ -484,7 +484,7 @@ Wei > + numa-node-id = <0>; > + }; > + -> + cpu11: cpu at 10203 { +> + cpu11: cpu@10203 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x10203>; @@ -493,7 +493,7 @@ Wei > + numa-node-id = <0>; > + }; > + -> + cpu12: cpu at 10300 { +> + cpu12: cpu@10300 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x10300>; @@ -502,7 +502,7 @@ Wei > + numa-node-id = <0>; > + }; > + -> + cpu13: cpu at 10301 { +> + cpu13: cpu@10301 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x10301>; @@ -511,7 +511,7 @@ Wei > + numa-node-id = <0>; > + }; > + -> + cpu14: cpu at 10302 { +> + cpu14: cpu@10302 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x10302>; @@ -520,7 +520,7 @@ Wei > + numa-node-id = <0>; > + }; > + -> + cpu15: cpu at 10303 { +> + cpu15: cpu@10303 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x10303>; @@ -529,7 +529,7 @@ Wei > + numa-node-id = <0>; > + }; > + -> + cpu16: cpu at 30000 { +> + cpu16: cpu@30000 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x30000>; @@ -538,7 +538,7 @@ Wei > + numa-node-id = <1>; > + }; > + -> + cpu17: cpu at 30001 { +> + cpu17: cpu@30001 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x30001>; @@ -547,7 +547,7 @@ Wei > + numa-node-id = <1>; > + }; > + -> + cpu18: cpu at 30002 { +> + cpu18: cpu@30002 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x30002>; @@ -556,7 +556,7 @@ Wei > + numa-node-id = <1>; > + }; > + -> + cpu19: cpu at 30003 { +> + cpu19: cpu@30003 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x30003>; @@ -565,7 +565,7 @@ Wei > + numa-node-id = <1>; > + }; > + -> + cpu20: cpu at 30100 { +> + cpu20: cpu@30100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x30100>; @@ -574,7 +574,7 @@ Wei > + numa-node-id = <1>; > + }; > + -> + cpu21: cpu at 30101 { +> + cpu21: cpu@30101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x30101>; @@ -583,7 +583,7 @@ Wei > + numa-node-id = <1>; > + }; > + -> + cpu22: cpu at 30102 { +> + cpu22: cpu@30102 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x30102>; @@ -592,7 +592,7 @@ Wei > + numa-node-id = <1>; > + }; > + -> + cpu23: cpu at 30103 { +> + cpu23: cpu@30103 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x30103>; @@ -601,7 +601,7 @@ Wei > + numa-node-id = <1>; > + }; > + -> + cpu24: cpu at 30200 { +> + cpu24: cpu@30200 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x30200>; @@ -610,7 +610,7 @@ Wei > + numa-node-id = <1>; > + }; > + -> + cpu25: cpu at 30201 { +> + cpu25: cpu@30201 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x30201>; @@ -619,7 +619,7 @@ Wei > + numa-node-id = <1>; > + }; > + -> + cpu26: cpu at 30202 { +> + cpu26: cpu@30202 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x30202>; @@ -628,7 +628,7 @@ Wei > + numa-node-id = <1>; > + }; > + -> + cpu27: cpu at 30203 { +> + cpu27: cpu@30203 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x30203>; @@ -637,7 +637,7 @@ Wei > + numa-node-id = <1>; > + }; > + -> + cpu28: cpu at 30300 { +> + cpu28: cpu@30300 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x30300>; @@ -646,7 +646,7 @@ Wei > + numa-node-id = <1>; > + }; > + -> + cpu29: cpu at 30301 { +> + cpu29: cpu@30301 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x30301>; @@ -655,7 +655,7 @@ Wei > + numa-node-id = <1>; > + }; > + -> + cpu30: cpu at 30302 { +> + cpu30: cpu@30302 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x30302>; @@ -664,7 +664,7 @@ Wei > + numa-node-id = <1>; > + }; > + -> + cpu31: cpu at 30303 { +> + cpu31: cpu@30303 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x30303>; @@ -673,7 +673,7 @@ Wei > + numa-node-id = <1>; > + }; > + -> + cpu32: cpu at 50000 { +> + cpu32: cpu@50000 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x50000>; @@ -682,7 +682,7 @@ Wei > + numa-node-id = <2>; > + }; > + -> + cpu33: cpu at 50001 { +> + cpu33: cpu@50001 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x50001>; @@ -691,7 +691,7 @@ Wei > + numa-node-id = <2>; > + }; > + -> + cpu34: cpu at 50002 { +> + cpu34: cpu@50002 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x50002>; @@ -700,7 +700,7 @@ Wei > + numa-node-id = <2>; > + }; > + -> + cpu35: cpu at 50003 { +> + cpu35: cpu@50003 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x50003>; @@ -709,7 +709,7 @@ Wei > + numa-node-id = <2>; > + }; > + -> + cpu36: cpu at 50100 { +> + cpu36: cpu@50100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x50100>; @@ -718,7 +718,7 @@ Wei > + numa-node-id = <2>; > + }; > + -> + cpu37: cpu at 50101 { +> + cpu37: cpu@50101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x50101>; @@ -727,7 +727,7 @@ Wei > + numa-node-id = <2>; > + }; > + -> + cpu38: cpu at 50102 { +> + cpu38: cpu@50102 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x50102>; @@ -736,7 +736,7 @@ Wei > + numa-node-id = <2>; > + }; > + -> + cpu39: cpu at 50103 { +> + cpu39: cpu@50103 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x50103>; @@ -745,7 +745,7 @@ Wei > + numa-node-id = <2>; > + }; > + -> + cpu40: cpu at 50200 { +> + cpu40: cpu@50200 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x50200>; @@ -754,7 +754,7 @@ Wei > + numa-node-id = <2>; > + }; > + -> + cpu41: cpu at 50201 { +> + cpu41: cpu@50201 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x50201>; @@ -763,7 +763,7 @@ Wei > + numa-node-id = <2>; > + }; > + -> + cpu42: cpu at 50202 { +> + cpu42: cpu@50202 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x50202>; @@ -772,7 +772,7 @@ Wei > + numa-node-id = <2>; > + }; > + -> + cpu43: cpu at 50203 { +> + cpu43: cpu@50203 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x50203>; @@ -781,7 +781,7 @@ Wei > + numa-node-id = <2>; > + }; > + -> + cpu44: cpu at 50300 { +> + cpu44: cpu@50300 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x50300>; @@ -790,7 +790,7 @@ Wei > + numa-node-id = <2>; > + }; > + -> + cpu45: cpu at 50301 { +> + cpu45: cpu@50301 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x50301>; @@ -799,7 +799,7 @@ Wei > + numa-node-id = <2>; > + }; > + -> + cpu46: cpu at 50302 { +> + cpu46: cpu@50302 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x50302>; @@ -808,7 +808,7 @@ Wei > + numa-node-id = <2>; > + }; > + -> + cpu47: cpu at 50303 { +> + cpu47: cpu@50303 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x50303>; @@ -817,7 +817,7 @@ Wei > + numa-node-id = <2>; > + }; > + -> + cpu48: cpu at 70000 { +> + cpu48: cpu@70000 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x70000>; @@ -826,7 +826,7 @@ Wei > + numa-node-id = <3>; > + }; > + -> + cpu49: cpu at 70001 { +> + cpu49: cpu@70001 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x70001>; @@ -835,7 +835,7 @@ Wei > + numa-node-id = <3>; > + }; > + -> + cpu50: cpu at 70002 { +> + cpu50: cpu@70002 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x70002>; @@ -844,7 +844,7 @@ Wei > + numa-node-id = <3>; > + }; > + -> + cpu51: cpu at 70003 { +> + cpu51: cpu@70003 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x70003>; @@ -853,7 +853,7 @@ Wei > + numa-node-id = <3>; > + }; > + -> + cpu52: cpu at 70100 { +> + cpu52: cpu@70100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x70100>; @@ -862,7 +862,7 @@ Wei > + numa-node-id = <3>; > + }; > + -> + cpu53: cpu at 70101 { +> + cpu53: cpu@70101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x70101>; @@ -871,7 +871,7 @@ Wei > + numa-node-id = <3>; > + }; > + -> + cpu54: cpu at 70102 { +> + cpu54: cpu@70102 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x70102>; @@ -880,7 +880,7 @@ Wei > + numa-node-id = <3>; > + }; > + -> + cpu55: cpu at 70103 { +> + cpu55: cpu@70103 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x70103>; @@ -889,7 +889,7 @@ Wei > + numa-node-id = <3>; > + }; > + -> + cpu56: cpu at 70200 { +> + cpu56: cpu@70200 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x70200>; @@ -898,7 +898,7 @@ Wei > + numa-node-id = <3>; > + }; > + -> + cpu57: cpu at 70201 { +> + cpu57: cpu@70201 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x70201>; @@ -907,7 +907,7 @@ Wei > + numa-node-id = <3>; > + }; > + -> + cpu58: cpu at 70202 { +> + cpu58: cpu@70202 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x70202>; @@ -916,7 +916,7 @@ Wei > + numa-node-id = <3>; > + }; > + -> + cpu59: cpu at 70203 { +> + cpu59: cpu@70203 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x70203>; @@ -925,7 +925,7 @@ Wei > + numa-node-id = <3>; > + }; > + -> + cpu60: cpu at 70300 { +> + cpu60: cpu@70300 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x70300>; @@ -934,7 +934,7 @@ Wei > + numa-node-id = <3>; > + }; > + -> + cpu61: cpu at 70301 { +> + cpu61: cpu@70301 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x70301>; @@ -943,7 +943,7 @@ Wei > + numa-node-id = <3>; > + }; > + -> + cpu62: cpu at 70302 { +> + cpu62: cpu@70302 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x70302>; @@ -952,7 +952,7 @@ Wei > + numa-node-id = <3>; > + }; > + -> + cpu63: cpu at 70303 { +> + cpu63: cpu@70303 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x70303>; @@ -1026,7 +1026,7 @@ Wei > + }; > + }; > + -> + gic: interrupt-controller at 4d000000 { +> + gic: interrupt-controller@4d000000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + #address-cells = <2>; @@ -1045,56 +1045,56 @@ Wei > + <0x0 0xfe020000 0x0 0x10000>; /* GICV */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + -> + p0_its_peri_a: interrupt-controller at 4c000000 { +> + p0_its_peri_a: interrupt-controller@4c000000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + #msi-cells = <1>; > + reg = <0x0 0x4c000000 0x0 0x40000>; > + }; > + -> + p0_its_peri_b: interrupt-controller at 6c000000 { +> + p0_its_peri_b: interrupt-controller@6c000000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + #msi-cells = <1>; > + reg = <0x0 0x6c000000 0x0 0x40000>; > + }; > + -> + p0_its_dsa_a: interrupt-controller at c6000000 { +> + p0_its_dsa_a: interrupt-controller@c6000000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + #msi-cells = <1>; > + reg = <0x0 0xc6000000 0x0 0x40000>; > + }; > + -> + p0_its_dsa_b: interrupt-controller at 8,c6000000 { +> + p0_its_dsa_b: interrupt-controller@8,c6000000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + #msi-cells = <1>; > + reg = <0x8 0xc6000000 0x0 0x40000>; > + }; > + -> + p1_its_peri_a: interrupt-controller at 400,4c000000 { +> + p1_its_peri_a: interrupt-controller@400,4c000000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + #msi-cells = <1>; > + reg = <0x400 0x4c000000 0x0 0x40000>; > + }; > + -> + p1_its_peri_b: interrupt-controller at 400,6c000000 { +> + p1_its_peri_b: interrupt-controller@400,6c000000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + #msi-cells = <1>; > + reg = <0x400 0x6c000000 0x0 0x40000>; > + }; > + -> + p1_its_dsa_a: interrupt-controller at 400,c6000000 { +> + p1_its_dsa_a: interrupt-controller@400,c6000000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + #msi-cells = <1>; > + reg = <0x400 0xc6000000 0x0 0x40000>; > + }; > + -> + p1_its_dsa_b: interrupt-controller at 408,c6000000 { +> + p1_its_dsa_b: interrupt-controller@408,c6000000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + #msi-cells = <1>; @@ -1115,7 +1115,7 @@ Wei > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; > + }; > + -> + p0_mbigen_peri_b: interrupt-controller at 60080000 { +> + p0_mbigen_peri_b: interrupt-controller@60080000 { > + compatible = "hisilicon,mbigen-v2"; > + reg = <0x0 0x60080000 0x0 0x10000>; > + @@ -1127,7 +1127,7 @@ Wei > + }; > + }; > + -> + p0_mbigen_pcie_a: interrupt-controller at a0080000 { +> + p0_mbigen_pcie_a: interrupt-controller@a0080000 { > + compatible = "hisilicon,mbigen-v2"; > + reg = <0x0 0xa0080000 0x0 0x10000>; > + @@ -1145,7 +1145,7 @@ Wei > + #size-cells = <2>; > + ranges; > + -> + uart0: uart at 602b0000 { +> + uart0: uart@602b0000 { > + compatible = "arm,sbsa-uart"; > + reg = <0x0 0x602b0000 0x0 0x1000>; > + interrupt-parent = <&mbigen_uart>; @@ -1155,7 +1155,7 @@ Wei > + status = "disabled"; > + }; > + -> + usb_ohci: ohci at a7030000 { +> + usb_ohci: ohci@a7030000 { > + compatible = "generic-ohci"; > + reg = <0x0 0xa7030000 0x0 0x10000>; > + interrupt-parent = <&mbigen_usb>; @@ -1164,7 +1164,7 @@ Wei > + status = "disabled"; > + }; > + -> + usb_ehci: ehci at a7020000 { +> + usb_ehci: ehci@a7020000 { > + compatible = "generic-ehci"; > + reg = <0x0 0xa7020000 0x0 0x10000>; > + interrupt-parent = <&mbigen_usb>; diff --git a/a/content_digest b/N1/content_digest index 54e17e5..0be9b58 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,9 +1,17 @@ "ref\01474708465-38958-1-git-send-email-wangkefeng.wang@huawei.com\0" "ref\01474708465-38958-4-git-send-email-wangkefeng.wang@huawei.com\0" - "From\0xuwei5@hisilicon.com (Wei Xu)\0" - "Subject\0[PATCH 3/5] arm64: dts: hisilicon: Add initial dts for Hip07 D05 board\0" + "From\0Wei Xu <xuwei5@hisilicon.com>\0" + "Subject\0Re: [PATCH 3/5] arm64: dts: hisilicon: Add initial dts for Hip07 D05 board\0" "Date\0Tue, 15 Nov 2016 16:18:14 +0000\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Kefeng Wang <wangkefeng.wang@huawei.com>\0" + "Cc\0Rob Herring <robh+dt@kernel.org>" + Mark Rutland <mark.rutland@arm.com> + <linux-arm-kernel@lists.infradead.org> + Catalin Marinas <catalin.marinas@arm.com> + Will Deacon <will.deacon@arm.com> + <majun258@huawei.com> + <guohanjun@huawei.com> + " <linux-kernel@vger.kernel.org>\0" "\00:1\0" "b\0" "Hi Kefeng,\n" @@ -71,7 +79,7 @@ "> +\tcompatible = \"hisilicon,hip07-d05\";\n" "> +\n" "> +\t/* the mem node will be updated by UEFI. */\n" - "> +\tmemory at 0 {\n" + "> +\tmemory@0 {\n" "> +\t\tdevice_type = \"memory\";\n" "> +\t\treg = <0x0 0x00000000 0x0 0x40000000>;\n" "> +\t\tnuma-node-id = <0>;\n" @@ -393,7 +401,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu0: cpu at 10000 {\n" + "> +\t\tcpu0: cpu@10000 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x10000>;\n" @@ -402,7 +410,7 @@ "> +\t\t\tnuma-node-id = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu1: cpu at 10001 {\n" + "> +\t\tcpu1: cpu@10001 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x10001>;\n" @@ -411,7 +419,7 @@ "> +\t\t\tnuma-node-id = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu2: cpu at 10002 {\n" + "> +\t\tcpu2: cpu@10002 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x10002>;\n" @@ -420,7 +428,7 @@ "> +\t\t\tnuma-node-id = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu3: cpu at 10003 {\n" + "> +\t\tcpu3: cpu@10003 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x10003>;\n" @@ -429,7 +437,7 @@ "> +\t\t\tnuma-node-id = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu4: cpu at 10100 {\n" + "> +\t\tcpu4: cpu@10100 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x10100>;\n" @@ -438,7 +446,7 @@ "> +\t\t\tnuma-node-id = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu5: cpu at 10101 {\n" + "> +\t\tcpu5: cpu@10101 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x10101>;\n" @@ -447,7 +455,7 @@ "> +\t\t\tnuma-node-id = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu6: cpu at 10102 {\n" + "> +\t\tcpu6: cpu@10102 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x10102>;\n" @@ -456,7 +464,7 @@ "> +\t\t\tnuma-node-id = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu7: cpu at 10103 {\n" + "> +\t\tcpu7: cpu@10103 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x10103>;\n" @@ -465,7 +473,7 @@ "> +\t\t\tnuma-node-id = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu8: cpu at 10200 {\n" + "> +\t\tcpu8: cpu@10200 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x10200>;\n" @@ -474,7 +482,7 @@ "> +\t\t\tnuma-node-id = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu9: cpu at 10201 {\n" + "> +\t\tcpu9: cpu@10201 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x10201>;\n" @@ -483,7 +491,7 @@ "> +\t\t\tnuma-node-id = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu10: cpu at 10202 {\n" + "> +\t\tcpu10: cpu@10202 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x10202>;\n" @@ -492,7 +500,7 @@ "> +\t\t\tnuma-node-id = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu11: cpu at 10203 {\n" + "> +\t\tcpu11: cpu@10203 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x10203>;\n" @@ -501,7 +509,7 @@ "> +\t\t\tnuma-node-id = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu12: cpu at 10300 {\n" + "> +\t\tcpu12: cpu@10300 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x10300>;\n" @@ -510,7 +518,7 @@ "> +\t\t\tnuma-node-id = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu13: cpu at 10301 {\n" + "> +\t\tcpu13: cpu@10301 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x10301>;\n" @@ -519,7 +527,7 @@ "> +\t\t\tnuma-node-id = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu14: cpu at 10302 {\n" + "> +\t\tcpu14: cpu@10302 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x10302>;\n" @@ -528,7 +536,7 @@ "> +\t\t\tnuma-node-id = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu15: cpu at 10303 {\n" + "> +\t\tcpu15: cpu@10303 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x10303>;\n" @@ -537,7 +545,7 @@ "> +\t\t\tnuma-node-id = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu16: cpu at 30000 {\n" + "> +\t\tcpu16: cpu@30000 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x30000>;\n" @@ -546,7 +554,7 @@ "> +\t\t\tnuma-node-id = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu17: cpu at 30001 {\n" + "> +\t\tcpu17: cpu@30001 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x30001>;\n" @@ -555,7 +563,7 @@ "> +\t\t\tnuma-node-id = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu18: cpu at 30002 {\n" + "> +\t\tcpu18: cpu@30002 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x30002>;\n" @@ -564,7 +572,7 @@ "> +\t\t\tnuma-node-id = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu19: cpu at 30003 {\n" + "> +\t\tcpu19: cpu@30003 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x30003>;\n" @@ -573,7 +581,7 @@ "> +\t\t\tnuma-node-id = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu20: cpu at 30100 {\n" + "> +\t\tcpu20: cpu@30100 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x30100>;\n" @@ -582,7 +590,7 @@ "> +\t\t\tnuma-node-id = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu21: cpu at 30101 {\n" + "> +\t\tcpu21: cpu@30101 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x30101>;\n" @@ -591,7 +599,7 @@ "> +\t\t\tnuma-node-id = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu22: cpu at 30102 {\n" + "> +\t\tcpu22: cpu@30102 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x30102>;\n" @@ -600,7 +608,7 @@ "> +\t\t\tnuma-node-id = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu23: cpu at 30103 {\n" + "> +\t\tcpu23: cpu@30103 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x30103>;\n" @@ -609,7 +617,7 @@ "> +\t\t\tnuma-node-id = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu24: cpu at 30200 {\n" + "> +\t\tcpu24: cpu@30200 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x30200>;\n" @@ -618,7 +626,7 @@ "> +\t\t\tnuma-node-id = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu25: cpu at 30201 {\n" + "> +\t\tcpu25: cpu@30201 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x30201>;\n" @@ -627,7 +635,7 @@ "> +\t\t\tnuma-node-id = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu26: cpu at 30202 {\n" + "> +\t\tcpu26: cpu@30202 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x30202>;\n" @@ -636,7 +644,7 @@ "> +\t\t\tnuma-node-id = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu27: cpu at 30203 {\n" + "> +\t\tcpu27: cpu@30203 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x30203>;\n" @@ -645,7 +653,7 @@ "> +\t\t\tnuma-node-id = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu28: cpu at 30300 {\n" + "> +\t\tcpu28: cpu@30300 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x30300>;\n" @@ -654,7 +662,7 @@ "> +\t\t\tnuma-node-id = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu29: cpu at 30301 {\n" + "> +\t\tcpu29: cpu@30301 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x30301>;\n" @@ -663,7 +671,7 @@ "> +\t\t\tnuma-node-id = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu30: cpu at 30302 {\n" + "> +\t\tcpu30: cpu@30302 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x30302>;\n" @@ -672,7 +680,7 @@ "> +\t\t\tnuma-node-id = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu31: cpu at 30303 {\n" + "> +\t\tcpu31: cpu@30303 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x30303>;\n" @@ -681,7 +689,7 @@ "> +\t\t\tnuma-node-id = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu32: cpu at 50000 {\n" + "> +\t\tcpu32: cpu@50000 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x50000>;\n" @@ -690,7 +698,7 @@ "> +\t\t\tnuma-node-id = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu33: cpu at 50001 {\n" + "> +\t\tcpu33: cpu@50001 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x50001>;\n" @@ -699,7 +707,7 @@ "> +\t\t\tnuma-node-id = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu34: cpu at 50002 {\n" + "> +\t\tcpu34: cpu@50002 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x50002>;\n" @@ -708,7 +716,7 @@ "> +\t\t\tnuma-node-id = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu35: cpu at 50003 {\n" + "> +\t\tcpu35: cpu@50003 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x50003>;\n" @@ -717,7 +725,7 @@ "> +\t\t\tnuma-node-id = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu36: cpu at 50100 {\n" + "> +\t\tcpu36: cpu@50100 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x50100>;\n" @@ -726,7 +734,7 @@ "> +\t\t\tnuma-node-id = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu37: cpu at 50101 {\n" + "> +\t\tcpu37: cpu@50101 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x50101>;\n" @@ -735,7 +743,7 @@ "> +\t\t\tnuma-node-id = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu38: cpu at 50102 {\n" + "> +\t\tcpu38: cpu@50102 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x50102>;\n" @@ -744,7 +752,7 @@ "> +\t\t\tnuma-node-id = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu39: cpu at 50103 {\n" + "> +\t\tcpu39: cpu@50103 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x50103>;\n" @@ -753,7 +761,7 @@ "> +\t\t\tnuma-node-id = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu40: cpu at 50200 {\n" + "> +\t\tcpu40: cpu@50200 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x50200>;\n" @@ -762,7 +770,7 @@ "> +\t\t\tnuma-node-id = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu41: cpu at 50201 {\n" + "> +\t\tcpu41: cpu@50201 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x50201>;\n" @@ -771,7 +779,7 @@ "> +\t\t\tnuma-node-id = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu42: cpu at 50202 {\n" + "> +\t\tcpu42: cpu@50202 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x50202>;\n" @@ -780,7 +788,7 @@ "> +\t\t\tnuma-node-id = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu43: cpu at 50203 {\n" + "> +\t\tcpu43: cpu@50203 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x50203>;\n" @@ -789,7 +797,7 @@ "> +\t\t\tnuma-node-id = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu44: cpu at 50300 {\n" + "> +\t\tcpu44: cpu@50300 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x50300>;\n" @@ -798,7 +806,7 @@ "> +\t\t\tnuma-node-id = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu45: cpu at 50301 {\n" + "> +\t\tcpu45: cpu@50301 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x50301>;\n" @@ -807,7 +815,7 @@ "> +\t\t\tnuma-node-id = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu46: cpu at 50302 {\n" + "> +\t\tcpu46: cpu@50302 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x50302>;\n" @@ -816,7 +824,7 @@ "> +\t\t\tnuma-node-id = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu47: cpu at 50303 {\n" + "> +\t\tcpu47: cpu@50303 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x50303>;\n" @@ -825,7 +833,7 @@ "> +\t\t\tnuma-node-id = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu48: cpu at 70000 {\n" + "> +\t\tcpu48: cpu@70000 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x70000>;\n" @@ -834,7 +842,7 @@ "> +\t\t\tnuma-node-id = <3>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu49: cpu at 70001 {\n" + "> +\t\tcpu49: cpu@70001 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x70001>;\n" @@ -843,7 +851,7 @@ "> +\t\t\tnuma-node-id = <3>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu50: cpu at 70002 {\n" + "> +\t\tcpu50: cpu@70002 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x70002>;\n" @@ -852,7 +860,7 @@ "> +\t\t\tnuma-node-id = <3>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu51: cpu at 70003 {\n" + "> +\t\tcpu51: cpu@70003 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x70003>;\n" @@ -861,7 +869,7 @@ "> +\t\t\tnuma-node-id = <3>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu52: cpu at 70100 {\n" + "> +\t\tcpu52: cpu@70100 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x70100>;\n" @@ -870,7 +878,7 @@ "> +\t\t\tnuma-node-id = <3>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu53: cpu at 70101 {\n" + "> +\t\tcpu53: cpu@70101 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x70101>;\n" @@ -879,7 +887,7 @@ "> +\t\t\tnuma-node-id = <3>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu54: cpu at 70102 {\n" + "> +\t\tcpu54: cpu@70102 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x70102>;\n" @@ -888,7 +896,7 @@ "> +\t\t\tnuma-node-id = <3>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu55: cpu at 70103 {\n" + "> +\t\tcpu55: cpu@70103 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x70103>;\n" @@ -897,7 +905,7 @@ "> +\t\t\tnuma-node-id = <3>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu56: cpu at 70200 {\n" + "> +\t\tcpu56: cpu@70200 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x70200>;\n" @@ -906,7 +914,7 @@ "> +\t\t\tnuma-node-id = <3>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu57: cpu at 70201 {\n" + "> +\t\tcpu57: cpu@70201 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x70201>;\n" @@ -915,7 +923,7 @@ "> +\t\t\tnuma-node-id = <3>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu58: cpu at 70202 {\n" + "> +\t\tcpu58: cpu@70202 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x70202>;\n" @@ -924,7 +932,7 @@ "> +\t\t\tnuma-node-id = <3>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu59: cpu at 70203 {\n" + "> +\t\tcpu59: cpu@70203 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x70203>;\n" @@ -933,7 +941,7 @@ "> +\t\t\tnuma-node-id = <3>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu60: cpu at 70300 {\n" + "> +\t\tcpu60: cpu@70300 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x70300>;\n" @@ -942,7 +950,7 @@ "> +\t\t\tnuma-node-id = <3>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu61: cpu at 70301 {\n" + "> +\t\tcpu61: cpu@70301 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x70301>;\n" @@ -951,7 +959,7 @@ "> +\t\t\tnuma-node-id = <3>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu62: cpu at 70302 {\n" + "> +\t\tcpu62: cpu@70302 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x70302>;\n" @@ -960,7 +968,7 @@ "> +\t\t\tnuma-node-id = <3>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu63: cpu at 70303 {\n" + "> +\t\tcpu63: cpu@70303 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x70303>;\n" @@ -1034,7 +1042,7 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller at 4d000000 {\n" + "> +\tgic: interrupt-controller@4d000000 {\n" "> +\t\tcompatible = \"arm,gic-v3\";\n" "> +\t\t#interrupt-cells = <3>;\n" "> +\t\t#address-cells = <2>;\n" @@ -1053,56 +1061,56 @@ "> +\t\t <0x0 0xfe020000 0x0 0x10000>;\t/* GICV */\n" "> +\t\tinterrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;\n" "> +\n" - "> +\t\tp0_its_peri_a: interrupt-controller at 4c000000 {\n" + "> +\t\tp0_its_peri_a: interrupt-controller@4c000000 {\n" "> +\t\t\tcompatible = \"arm,gic-v3-its\";\n" "> +\t\t\tmsi-controller;\n" "> +\t\t\t#msi-cells = <1>;\n" "> +\t\t\treg = <0x0 0x4c000000 0x0 0x40000>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tp0_its_peri_b: interrupt-controller at 6c000000 {\n" + "> +\t\tp0_its_peri_b: interrupt-controller@6c000000 {\n" "> +\t\t\tcompatible = \"arm,gic-v3-its\";\n" "> +\t\t\tmsi-controller;\n" "> +\t\t\t#msi-cells = <1>;\n" "> +\t\t\treg = <0x0 0x6c000000 0x0 0x40000>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tp0_its_dsa_a: interrupt-controller at c6000000 {\n" + "> +\t\tp0_its_dsa_a: interrupt-controller@c6000000 {\n" "> +\t\t\tcompatible = \"arm,gic-v3-its\";\n" "> +\t\t\tmsi-controller;\n" "> +\t\t\t#msi-cells = <1>;\n" "> +\t\t\treg = <0x0 0xc6000000 0x0 0x40000>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tp0_its_dsa_b: interrupt-controller at 8,c6000000 {\n" + "> +\t\tp0_its_dsa_b: interrupt-controller@8,c6000000 {\n" "> +\t\t\tcompatible = \"arm,gic-v3-its\";\n" "> +\t\t\tmsi-controller;\n" "> +\t\t\t#msi-cells = <1>;\n" "> +\t\t\treg = <0x8 0xc6000000 0x0 0x40000>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tp1_its_peri_a: interrupt-controller at 400,4c000000 {\n" + "> +\t\tp1_its_peri_a: interrupt-controller@400,4c000000 {\n" "> +\t\t\tcompatible = \"arm,gic-v3-its\";\n" "> +\t\t\tmsi-controller;\n" "> +\t\t\t#msi-cells = <1>;\n" "> +\t\t\treg = <0x400 0x4c000000 0x0 0x40000>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tp1_its_peri_b: interrupt-controller at 400,6c000000 {\n" + "> +\t\tp1_its_peri_b: interrupt-controller@400,6c000000 {\n" "> +\t\t\tcompatible = \"arm,gic-v3-its\";\n" "> +\t\t\tmsi-controller;\n" "> +\t\t\t#msi-cells = <1>;\n" "> +\t\t\treg = <0x400 0x6c000000 0x0 0x40000>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tp1_its_dsa_a: interrupt-controller at 400,c6000000 {\n" + "> +\t\tp1_its_dsa_a: interrupt-controller@400,c6000000 {\n" "> +\t\t\tcompatible = \"arm,gic-v3-its\";\n" "> +\t\t\tmsi-controller;\n" "> +\t\t\t#msi-cells = <1>;\n" "> +\t\t\treg = <0x400 0xc6000000 0x0 0x40000>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tp1_its_dsa_b: interrupt-controller at 408,c6000000 {\n" + "> +\t\tp1_its_dsa_b: interrupt-controller@408,c6000000 {\n" "> +\t\t\tcompatible = \"arm,gic-v3-its\";\n" "> +\t\t\tmsi-controller;\n" "> +\t\t\t#msi-cells = <1>;\n" @@ -1123,7 +1131,7 @@ "> +\t\tinterrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;\n" "> +\t};\n" "> +\n" - "> +\tp0_mbigen_peri_b: interrupt-controller at 60080000 {\n" + "> +\tp0_mbigen_peri_b: interrupt-controller@60080000 {\n" "> +\t\tcompatible = \"hisilicon,mbigen-v2\";\n" "> +\t\treg = <0x0 0x60080000 0x0 0x10000>;\n" "> +\n" @@ -1135,7 +1143,7 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tp0_mbigen_pcie_a: interrupt-controller at a0080000 {\n" + "> +\tp0_mbigen_pcie_a: interrupt-controller@a0080000 {\n" "> +\t\tcompatible = \"hisilicon,mbigen-v2\";\n" "> +\t\treg = <0x0 0xa0080000 0x0 0x10000>;\n" "> +\n" @@ -1153,7 +1161,7 @@ "> +\t\t#size-cells = <2>;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tuart0: uart at 602b0000 {\n" + "> +\t\tuart0: uart@602b0000 {\n" "> +\t\t\tcompatible = \"arm,sbsa-uart\";\n" "> +\t\t\treg = <0x0 0x602b0000 0x0 0x1000>;\n" "> +\t\t\tinterrupt-parent = <&mbigen_uart>;\n" @@ -1163,7 +1171,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tusb_ohci: ohci at a7030000 {\n" + "> +\t\tusb_ohci: ohci@a7030000 {\n" "> +\t\t\tcompatible = \"generic-ohci\";\n" "> +\t\t\treg = <0x0 0xa7030000 0x0 0x10000>;\n" "> +\t\t\tinterrupt-parent = <&mbigen_usb>;\n" @@ -1172,7 +1180,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tusb_ehci: ehci at a7020000 {\n" + "> +\t\tusb_ehci: ehci@a7020000 {\n" "> +\t\t\tcompatible = \"generic-ehci\";\n" "> +\t\t\treg = <0x0 0xa7020000 0x0 0x10000>;\n" "> +\t\t\tinterrupt-parent = <&mbigen_usb>;\n" @@ -1184,4 +1192,4 @@ "> +};\n" > -30ee0bd50cbad2221804698e329480297a0f0b358e9d606c65dca808ae753ddc +9c1dada6bd337406191bf0dee58e2b9d66721d56222065f7b15396cff2c1d345
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.