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[213.161.3.76]) by smtp.gmail.com with ESMTPSA id s16-20020a170906455000b00722bc0aa9e3sm8201642ejq.162.2022.07.04.10.34.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jul 2022 10:34:44 -0700 (PDT) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Roman Stratiienko Cc: Samuel Holland , =?ISO-8859-1?Q?Cl=E9ment_P=E9ron?= , Michael Turquette , sboyd@kernel.org, mripard@kernel.org, wens@csie.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: Re: [PATCH v2] clk: sunxi-ng: sun50i: h6: Modify GPU clock configuration to support DFS Date: Mon, 04 Jul 2022 19:34:43 +0200 Message-ID: <5835545.lOV4Wx5bFT@kista> In-Reply-To: References: <20220703164514.308622-1-r.stratiienko@gmail.com> <4748270.31r3eYUQgx@jernej-laptop> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Dne ponedeljek, 04. julij 2022 ob 11:54:06 CEST je Roman Stratiienko=20 napisal(a): > Hi Jernej, >=20 > =D0=B2=D1=81, 3 =D0=B8=D1=8E=D0=BB. 2022 =D0=B3. =D0=B2 21:43, Jernej =C5= =A0krabec : > > > > Dne nedelja, 03. julij 2022 ob 18:45:14 CEST je Roman Stratiienko=20 napisal(a): > > > Using simple bash script it was discovered that not all CCU registers > > > can be safely used for DFS, e.g.: > > > > > > while true > > > do > > > devmem 0x3001030 4 0xb0003e02 > > > devmem 0x3001030 4 0xb0001e02 > > > done > > > > > > Script above changes the GPU_PLL multiplier register value. While the > > > script is running, the user should interact with the user interface. > > > > > > Using this method the following results were obtained: > > > | Register | Name | Bits | Values | Result | > > > | -- | -- | -- | -- | -- | > > > | 0x3001030 | GPU_PLL.MULT | 15..8 | 20-62 | OK | > > > | 0x3001030 | GPU_PLL.INDIV | 1 | 0-1 | OK | > > > | 0x3001030 | GPU_PLL.OUTDIV | 0 | 0-1 | FAIL | > > > | 0x3001670 | GPU_CLK.DIV | 3..0 | ANY | FAIL | > > > > > > DVFS started to work seamlessly once dividers which caused the > > > glitches were set to fixed values. > > > > > > Signed-off-by: Roman Stratiienko > > > > > > --- > > > > > > Changelog: > > > > > > V2: > > > - Drop changes related to mux > > > - Drop frequency limiting > > > - Add unused dividers initialization > > > --- > > > drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 16 +++++++++++++--- > > > 1 file changed, 13 insertions(+), 3 deletions(-) > > > > > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c > > > b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c index 2ddf0a0da526f..1b0205ff2= 4108 > > > 100644 > > > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c > > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c > > > @@ -95,13 +95,13 @@ static struct ccu_nkmp pll_periph1_clk =3D { > > > }, > > > }; > > > > > > +/* For GPU PLL, using an output divider for DFS causes system to fai= l=20 */ > > > #define SUN50I_H6_PLL_GPU_REG 0x030 > > > static struct ccu_nkmp pll_gpu_clk =3D { > > > .enable =3D BIT(31), > > > .lock =3D BIT(28), > > > .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 12), > > > .m =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ > > > - .p =3D _SUNXI_CCU_DIV(0, 1), /* output divider > > */ > > > > Having minimum (288 MHz) as per vendor GPU driver and maximum, either m= ax.=20 opp > > or max. from datasheet is equally good. I know that both are basically= =20 limited > > with opp table, but people like to play with these, so it's good to hav= e=20 them > > in. > > > > > .common =3D { > > > .reg =3D 0x030, > > > .hw.init =3D CLK_HW_INIT("pll-gpu", "osc24M", > > > @@ -294,9 +294,9 @@ static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, > > > "deinterlace", static SUNXI_CCU_GATE(bus_deinterlace_clk, > > > "bus-deinterlace", "psi-ahb1-ahb2", 0x62c, BIT(0), 0); > > > > > > +/* Keep GPU_CLK divider const to avoid DFS instability. */ > > > static const char * const gpu_parents[] =3D { "pll-gpu" }; > > > -static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670, > > > - 0, 3, /* M */ > > > +static SUNXI_CCU_MUX_WITH_GATE(gpu_clk, "gpu", gpu_parents, 0x670, > > > 24, 1, /* mux */ > > > BIT(31), /* gate */ > > > CLK_SET_RATE_PARENT); > > > @@ -1193,6 +1193,16 @@ static int sun50i_h6_ccu_probe(struct=20 platform_device > > > *pdev) if (IS_ERR(reg)) > > > return PTR_ERR(reg); > > > > > > + /* Force PLL_GPU output divider to 0 */ > > > > Divider 0 here > > > > > + val =3D readl(reg + SUN50I_H6_PLL_GPU_REG); > > > + val &=3D ~BIT(0); > > > + writel(val, reg + SUN50I_H6_PLL_GPU_REG); > > > + > > > + /* Force GPU_CLK divider to 0 */ > > > > and here sounds wrong, since division by zero is not defined. Using 1 i= s=20 more > > intuitive and correct, since that's what HW actually uses. > > >=20 > You're right but a few lines below there is already a similar message > (see below) , so I used similar formulation to avoid confusion. Right. But there is another block of code below: /* * Force the post-divider of pll-audio to 12 and the output divider * of it to 2, so 24576000 and 22579200 rates can be set exactly. */ =2E.. writel(val | (11 << 16) | BIT(0), reg + SUN50I_H6_PLL_AUDIO_REG); Let's follow better practice. Eventually video PLL comment should be fixed = by=20 somebody. >=20 > /* > * Force the output divider of video PLLs to 0. > * > * See the comment before pll-video0 definition for the reason. > */ >=20 > > Patch looks good otherwise. >=20 > May I have your r-b? Yes. Best regards, Jernej >=20 > Best regards, > Roman >=20 > > > > Best regards, > > Jernej > > > > > + val =3D readl(reg + gpu_clk.common.reg); > > > + val &=3D ~GENMASK(3, 0); > > > + writel(val, reg + gpu_clk.common.reg); > > > + > > > /* Enable the lock bits on all PLLs */ > > > for (i =3D 0; i < ARRAY_SIZE(pll_regs); i++) { > > > val =3D readl(reg + pll_regs[i]); > > > > > > > > >=20 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7D795C433EF for ; Mon, 4 Jul 2022 17:35:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=yFbQfwEbtxUqdc3ocKar+FpRC6eVap/mkaDinhbHEk0=; b=c41qMCOpJExfst k7ODYK4JPxaK4fkKG44S/amZHXjD54WrAB37pxAHczHwNzJfr7EogVZdj46jJxbXJQmEPBI46UW0j /NztavtvhudehZ1eosl0kXgVrTGB/+oUhKgKhTxJvE8D+dKIS4exq/2gVCFboHRm+Ayw+/n+irdJN XnQDUOHD8IwCUKNxkuxQ5dhxrSMS7ADXJYHWDnAKEA2l7IL7/WqvnjBBfuR+qa/adBVeCx5sx4P7g IFcUyHjX5i5c8kwITTnrBQPnFbZhX/PD/JdG00WRG3aPxIEhwqwHWRmxXNU7pSKRMqwJl1Sp9tUus awa0YZP5llhBdCq64Kfg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8PyI-00AMc0-I6; Mon, 04 Jul 2022 17:34:54 +0000 Received: from mail-ej1-x62a.google.com ([2a00:1450:4864:20::62a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8PyE-00AMYY-IN for linux-arm-kernel@lists.infradead.org; Mon, 04 Jul 2022 17:34:52 +0000 Received: by mail-ej1-x62a.google.com with SMTP id mf9so17926066ejb.0 for ; Mon, 04 Jul 2022 10:34:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ntBm6YCFWqLI4Jifkq6aFgvski3omE1H3bv/CSOM6qc=; b=GBdC6pzu8EVPLJsIQoXp6zsx2jlrJ1iJYDMhew3YhI2Qnefslog6Cdt9VHCB1jXfhx Kl83bPB0vUeztwq4AxjwuigD4W2P042Q3AhnfVpPkgWhaeUFFFXOhdtJ9s2iIC2C2Myk 7O3dUitydNGfxsHYB1Iyi6DWJII9j8zO/Qyr7+/uCoxobq/B8tK2FFY3Pc7v/OsQQ0sd sy4Els9NRE3Cc0PnWIGs4pHhjc0HX6RREyczs9FAE86SrAqJdRKvRg3NoqPQSSRFAvSz kkK3DjCrcnazJnXRxFms5KnshcklxLNX5g+uNsfzy02Ioleh5mjOZb5YjIhvt4qJwCHG sdvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ntBm6YCFWqLI4Jifkq6aFgvski3omE1H3bv/CSOM6qc=; b=MYSe6jhvFH5VdzznAjb0qjIUFriGXUIi9OuibrqifbQsKZzaqwwC7FVtPW7OUaNxF+ uF/S5c+UNYCS7bzL6cjfskgJ8DJf+0qg6jjDBx48dItNJkV7zn7U2Bzk4ZjNFwaxt0de 9FlRpXrbvkaqyde7Yo52QoU6Ji0JTXExi43HfjbLtLlNfjzdKe1qdGQdEBsZy4gQ5tls bxBmGuJ6YxBXllpcTC6cNpv0xpHS6Up5gOg/uZDmxuUSf/6FThm7h1vTI+Fzmf0S5UU7 jJRCxU6Hqq14p35uGw+0UqGqYRW38MwdjD/uwSJfSiH+143zw0TT2VuHQhC/jWFfqDf4 xc0g== X-Gm-Message-State: AJIora9+ocIOzlOLZUVtLFwweVXZsQ13KDSsISaojke9j1YoTDlPyTAf x4gBzd7Xs5BuwYQ6G6SdmC0= X-Google-Smtp-Source: AGRyM1tzYdkegf4LD5FIRjzUzy9j+x4YZaeYS0wfjBi2wCjFHJYvDlyuaC02znpDLDcaFLbuQAwtng== X-Received: by 2002:a17:906:5055:b0:6ff:1dfb:1e2c with SMTP id e21-20020a170906505500b006ff1dfb1e2cmr13791384ejk.200.1656956085385; Mon, 04 Jul 2022 10:34:45 -0700 (PDT) Received: from kista.localnet (213-161-3-76.dynamic.telemach.net. [213.161.3.76]) by smtp.gmail.com with ESMTPSA id s16-20020a170906455000b00722bc0aa9e3sm8201642ejq.162.2022.07.04.10.34.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jul 2022 10:34:44 -0700 (PDT) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Roman Stratiienko Cc: Samuel Holland , =?ISO-8859-1?Q?Cl=E9ment_P=E9ron?= , Michael Turquette , sboyd@kernel.org, mripard@kernel.org, wens@csie.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: Re: [PATCH v2] clk: sunxi-ng: sun50i: h6: Modify GPU clock configuration to support DFS Date: Mon, 04 Jul 2022 19:34:43 +0200 Message-ID: <5835545.lOV4Wx5bFT@kista> In-Reply-To: References: <20220703164514.308622-1-r.stratiienko@gmail.com> <4748270.31r3eYUQgx@jernej-laptop> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220704_103450_667925_B3442D71 X-CRM114-Status: GOOD ( 36.13 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eGIwMDAzZTAyCj4gPiA+ICAgICAgICAgZGV2bWVtIDB4MzAwMTAzMCA0IDB4YjAwMDFlMDIKPiA+ ID4gICAgIGRvbmUKPiA+ID4KPiA+ID4gU2NyaXB0IGFib3ZlIGNoYW5nZXMgdGhlIEdQVV9QTEwg bXVsdGlwbGllciByZWdpc3RlciB2YWx1ZS4gV2hpbGUgdGhlCj4gPiA+IHNjcmlwdCBpcyBydW5u aW5nLCB0aGUgdXNlciBzaG91bGQgaW50ZXJhY3Qgd2l0aCB0aGUgdXNlciBpbnRlcmZhY2UuCj4g PiA+Cj4gPiA+IFVzaW5nIHRoaXMgbWV0aG9kIHRoZSBmb2xsb3dpbmcgcmVzdWx0cyB3ZXJlIG9i dGFpbmVkOgo+ID4gPiB8IFJlZ2lzdGVyICB8IE5hbWUgICAgICAgICAgIHwgQml0cyAgfCBWYWx1 ZXMgfCBSZXN1bHQgfAo+ID4gPiB8IC0tICAgICAgICB8IC0tICAgICAgICAgICAgIHwgLS0gICAg fCAtLSAgICAgfCAtLSAgICAgfAo+ID4gPiB8IDB4MzAwMTAzMCB8IEdQVV9QTEwuTVVMVCAgIHwg MTUuLjggfCAyMC02MiAgfCBPSyAgICAgfAo+ID4gPiB8IDB4MzAwMTAzMCB8IEdQVV9QTEwuSU5E SVYgIHwgICAgIDEgfCAwLTEgICAgfCBPSyAgICAgfAo+ID4gPiB8IDB4MzAwMTAzMCB8IEdQVV9Q TEwuT1VURElWIHwgICAgIDAgfCAwLTEgICAgfCBGQUlMICAgfAo+ID4gPiB8IDB4MzAwMTY3MCB8 IEdQVV9DTEsuRElWICAgIHwgIDMuLjAgfCBBTlkgICAgfCBGQUlMICAgfAo+ID4gPgo+ID4gPiBE VkZTIHN0YXJ0ZWQgdG8gd29yayBzZWFtbGVzc2x5IG9uY2UgZGl2aWRlcnMgd2hpY2ggY2F1c2Vk IHRoZQo+ID4gPiBnbGl0Y2hlcyB3ZXJlIHNldCB0byBmaXhlZCB2YWx1ZXMuCj4gPiA+Cj4gPiA+ IFNpZ25lZC1vZmYtYnk6IFJvbWFuIFN0cmF0aWllbmtvIDxyLnN0cmF0aWllbmtvQGdtYWlsLmNv bT4KPiA+ID4KPiA+ID4gLS0tCj4gPiA+Cj4gPiA+IENoYW5nZWxvZzoKPiA+ID4KPiA+ID4gVjI6 Cj4gPiA+IC0gRHJvcCBjaGFuZ2VzIHJlbGF0ZWQgdG8gbXV4Cj4gPiA+IC0gRHJvcCBmcmVxdWVu Y3kgbGltaXRpbmcKPiA+ID4gLSBBZGQgdW51c2VkIGRpdmlkZXJzIGluaXRpYWxpemF0aW9uCj4g PiA+IC0tLQo+ID4gPiAgZHJpdmVycy9jbGsvc3VueGktbmcvY2N1LXN1bjUwaS1oNi5jIHwgMTYg KysrKysrKysrKysrKy0tLQo+ID4gPiAgMSBmaWxlIGNoYW5nZWQsIDEzIGluc2VydGlvbnMoKyks IDMgZGVsZXRpb25zKC0pCj4gPiA+Cj4gPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2Nsay9zdW54 aS1uZy9jY3Utc3VuNTBpLWg2LmMKPiA+ID4gYi9kcml2ZXJzL2Nsay9zdW54aS1uZy9jY3Utc3Vu NTBpLWg2LmMgaW5kZXggMmRkZjBhMGRhNTI2Zi4uMWIwMjA1ZmYyNDEwOAo+ID4gPiAxMDA2NDQK PiA+ID4gLS0tIGEvZHJpdmVycy9jbGsvc3VueGktbmcvY2N1LXN1bjUwaS1oNi5jCj4gPiA+ICsr KyBiL2RyaXZlcnMvY2xrL3N1bnhpLW5nL2NjdS1zdW41MGktaDYuYwo+ID4gPiBAQCAtOTUsMTMg Kzk1LDEzIEBAIHN0YXRpYyBzdHJ1Y3QgY2N1X25rbXAgcGxsX3BlcmlwaDFfY2xrID0gewo+ID4g PiAgICAgICB9LAo+ID4gPiAgfTsKPiA+ID4KPiA+ID4gKy8qIEZvciBHUFUgUExMLCB1c2luZyBh biBvdXRwdXQgZGl2aWRlciBmb3IgREZTIGNhdXNlcyBzeXN0ZW0gdG8gZmFpbCAKKi8KPiA+ID4g ICNkZWZpbmUgU1VONTBJX0g2X1BMTF9HUFVfUkVHICAgICAgICAgICAgICAgIDB4MDMwCj4gPiA+ ICBzdGF0aWMgc3RydWN0IGNjdV9ua21wIHBsbF9ncHVfY2xrID0gewo+ID4gPiAgICAgICAuZW5h YmxlICAgICAgICAgPSBCSVQoMzEpLAo+ID4gPiAgICAgICAubG9jayAgICAgICAgICAgPSBCSVQo MjgpLAo+ID4gPiAgICAgICAubiAgICAgICAgICAgICAgPSBfU1VOWElfQ0NVX01VTFRfTUlOKDgs IDgsIDEyKSwKPiA+ID4gICAgICAgLm0gICAgICAgICAgICAgID0gX1NVTlhJX0NDVV9ESVYoMSwg MSksIC8qIGlucHV0IGRpdmlkZXIgKi8KPiA+ID4gLSAgICAgLnAgICAgICAgICAgICAgID0gX1NV TlhJX0NDVV9ESVYoMCwgMSksIC8qIG91dHB1dCBkaXZpZGVyCj4gPiAqLwo+ID4KPiA+IEhhdmlu ZyBtaW5pbXVtICgyODggTUh6KSBhcyBwZXIgdmVuZG9yIEdQVSBkcml2ZXIgYW5kIG1heGltdW0s IGVpdGhlciBtYXguIApvcHAKPiA+IG9yIG1heC4gZnJvbSBkYXRhc2hlZXQgaXMgZXF1YWxseSBn b29kLiBJIGtub3cgdGhhdCBib3RoIGFyZSBiYXNpY2FsbHkgCmxpbWl0ZWQKPiA+IHdpdGggb3Bw IHRhYmxlLCBidXQgcGVvcGxlIGxpa2UgdG8gcGxheSB3aXRoIHRoZXNlLCBzbyBpdCdzIGdvb2Qg dG8gaGF2ZSAKdGhlbQo+ID4gaW4uCj4gPgo+ID4gPiAgICAgICAuY29tbW9uICAgICAgICAgPSB7 Cj4gPiA+ICAgICAgICAgICAgICAgLnJlZyAgICAgICAgICAgID0gMHgwMzAsCj4gPiA+ICAgICAg ICAgICAgICAgLmh3LmluaXQgICAgICAgID0gQ0xLX0hXX0lOSVQoInBsbC1ncHUiLCAib3NjMjRN IiwKPiA+ID4gQEAgLTI5NCw5ICsyOTQsOSBAQCBzdGF0aWMgU1VOWElfQ0NVX01fV0lUSF9NVVhf R0FURShkZWludGVybGFjZV9jbGssCj4gPiA+ICJkZWludGVybGFjZSIsIHN0YXRpYyBTVU5YSV9D Q1VfR0FURShidXNfZGVpbnRlcmxhY2VfY2xrLAo+ID4gPiAiYnVzLWRlaW50ZXJsYWNlIiwgInBz aS1haGIxLWFoYjIiLCAweDYyYywgQklUKDApLCAwKTsKPiA+ID4KPiA+ID4gKy8qIEtlZXAgR1BV X0NMSyBkaXZpZGVyIGNvbnN0IHRvIGF2b2lkIERGUyBpbnN0YWJpbGl0eS4gKi8KPiA+ID4gIHN0 YXRpYyBjb25zdCBjaGFyICogY29uc3QgZ3B1X3BhcmVudHNbXSA9IHsgInBsbC1ncHUiIH07Cj4g PiA+IC1zdGF0aWMgU1VOWElfQ0NVX01fV0lUSF9NVVhfR0FURShncHVfY2xrLCAiZ3B1IiwgZ3B1 X3BhcmVudHMsIDB4NjcwLAo+ID4gPiAtICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgMCwgMywgICAgLyogTSAqLwo+ID4gPiArc3RhdGljIFNVTlhJX0NDVV9NVVhfV0lUSF9HQVRF KGdwdV9jbGssICJncHUiLCBncHVfcGFyZW50cywgMHg2NzAsCj4gPiA+ICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAyNCwgMSwgICAvKiBtdXggKi8KPiA+ID4gICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgIEJJVCgzMSksIC8qIGdhdGUgKi8KPiA+ID4gICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIENMS19TRVRfUkFURV9QQVJFTlQpOwo+ ID4gPiBAQCAtMTE5Myw2ICsxMTkzLDE2IEBAIHN0YXRpYyBpbnQgc3VuNTBpX2g2X2NjdV9wcm9i ZShzdHJ1Y3QgCnBsYXRmb3JtX2RldmljZQo+ID4gPiAqcGRldikgaWYgKElTX0VSUihyZWcpKQo+ ID4gPiAgICAgICAgICAgICAgIHJldHVybiBQVFJfRVJSKHJlZyk7Cj4gPiA+Cj4gPiA+ICsgICAg IC8qIEZvcmNlIFBMTF9HUFUgb3V0cHV0IGRpdmlkZXIgdG8gMCAqLwo+ID4KPiA+IERpdmlkZXIg IDAgaGVyZQo+ID4KPiA+ID4gKyAgICAgdmFsID0gcmVhZGwocmVnICsgU1VONTBJX0g2X1BMTF9H UFVfUkVHKTsKPiA+ID4gKyAgICAgdmFsICY9IH5CSVQoMCk7Cj4gPiA+ICsgICAgIHdyaXRlbCh2 YWwsIHJlZyArIFNVTjUwSV9INl9QTExfR1BVX1JFRyk7Cj4gPiA+ICsKPiA+ID4gKyAgICAgLyog Rm9yY2UgR1BVX0NMSyBkaXZpZGVyIHRvIDAgKi8KPiA+Cj4gPiBhbmQgaGVyZSBzb3VuZHMgd3Jv bmcsIHNpbmNlIGRpdmlzaW9uIGJ5IHplcm8gaXMgbm90IGRlZmluZWQuIFVzaW5nIDEgaXMgCm1v cmUKPiA+IGludHVpdGl2ZSBhbmQgY29ycmVjdCwgc2luY2UgdGhhdCdzIHdoYXQgSFcgYWN0dWFs bHkgdXNlcy4KPiA+Cj4gCj4gWW91J3JlIHJpZ2h0IGJ1dCBhIGZldyBsaW5lcyBiZWxvdyB0aGVy ZSBpcyBhbHJlYWR5IGEgc2ltaWxhciBtZXNzYWdlCj4gKHNlZSBiZWxvdykgLCBzbyBJIHVzZWQg c2ltaWxhciBmb3JtdWxhdGlvbiB0byBhdm9pZCBjb25mdXNpb24uCgpSaWdodC4gQnV0IHRoZXJl IGlzIGFub3RoZXIgYmxvY2sgb2YgY29kZSBiZWxvdzoKCi8qCiAqIEZvcmNlIHRoZSBwb3N0LWRp dmlkZXIgb2YgcGxsLWF1ZGlvIHRvIDEyIGFuZCB0aGUgb3V0cHV0IGRpdmlkZXIKICogb2YgaXQg dG8gMiwgc28gMjQ1NzYwMDAgYW5kIDIyNTc5MjAwIHJhdGVzIGNhbiBiZSBzZXQgZXhhY3RseS4K ICovCi4uLgp3cml0ZWwodmFsIHwgKDExIDw8IDE2KSB8IEJJVCgwKSwgcmVnICsgU1VONTBJX0g2 X1BMTF9BVURJT19SRUcpOwoKTGV0J3MgZm9sbG93IGJldHRlciBwcmFjdGljZS4gRXZlbnR1YWxs eSB2aWRlbyBQTEwgY29tbWVudCBzaG91bGQgYmUgZml4ZWQgYnkgCnNvbWVib2R5LgoKPiAKPiAg ICAgICAgIC8qCj4gICAgICAgICAgKiBGb3JjZSB0aGUgb3V0cHV0IGRpdmlkZXIgb2YgdmlkZW8g UExMcyB0byAwLgo+ICAgICAgICAgICoKPiAgICAgICAgICAqIFNlZSB0aGUgY29tbWVudCBiZWZv cmUgcGxsLXZpZGVvMCBkZWZpbml0aW9uIGZvciB0aGUgcmVhc29uLgo+ICAgICAgICAgICovCj4g Cj4gPiBQYXRjaCBsb29rcyBnb29kIG90aGVyd2lzZS4KPiAKPiBNYXkgSSBoYXZlIHlvdXIgci1i PwoKWWVzLgoKQmVzdCByZWdhcmRzLApKZXJuZWoKCj4gCj4gQmVzdCByZWdhcmRzLAo+IFJvbWFu Cj4gCj4gPgo+ID4gQmVzdCByZWdhcmRzLAo+ID4gSmVybmVqCj4gPgo+ID4gPiArICAgICB2YWwg PSByZWFkbChyZWcgKyBncHVfY2xrLmNvbW1vbi5yZWcpOwo+ID4gPiArICAgICB2YWwgJj0gfkdF Tk1BU0soMywgMCk7Cj4gPiA+ICsgICAgIHdyaXRlbCh2YWwsIHJlZyArIGdwdV9jbGsuY29tbW9u LnJlZyk7Cj4gPiA+ICsKPiA+ID4gICAgICAgLyogRW5hYmxlIHRoZSBsb2NrIGJpdHMgb24gYWxs IFBMTHMgKi8KPiA+ID4gICAgICAgZm9yIChpID0gMDsgaSA8IEFSUkFZX1NJWkUocGxsX3JlZ3Mp OyBpKyspIHsKPiA+ID4gICAgICAgICAgICAgICB2YWwgPSByZWFkbChyZWcgKyBwbGxfcmVnc1tp XSk7Cj4gPgo+ID4KPiA+Cj4gPgo+IAoKCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fXwpsaW51eC1hcm0ta2VybmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0t a2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFp bG1hbi9saXN0aW5mby9saW51eC1hcm0ta2VybmVsCg==