Re: [PATCH 4/7] drm/amdgpu/ih7.0: Use IH_SW_RING_SIZE for soft IH ring instead of PAGE_SIZE

["Timur Kristóf" <timur.kristof@gmail.com>]

On 2026. június 24., szerda 16:37:11 közép-európai nyári idő Tvrtko Ursulin 
wrote:
> On 29/05/2026 11:30, Timur Kristóf wrote:
> > When there are a lot of retry faults happening, the soft IH ring
> > can fill up really quickly and possibly overflow. PAGE_SIZE was
> > too small, use IH_SW_RING_SIZE to match what other GPU generations
> > are doing.
> > 
> > Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> > ---
> > 
> >   drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 5 +----
> >   1 file changed, 1 insertion(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
> > b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c index 4e6d14facf93a..ec0919fa82540
> > 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
> > @@ -587,7 +587,6 @@ static int ih_v7_0_sw_init(struct amdgpu_ip_block
> > *ip_block)> 
> >   	int r;
> >   	struct amdgpu_device *adev = ip_block->adev;
> >   	bool use_bus_addr;
> > 
> > -	unsigned int sw_ring_size;
> > 
> >   	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_IH, 0,
> >   	
> >   			      &adev->irq.self_irq);
> > 
> > @@ -619,9 +618,7 @@ static int ih_v7_0_sw_init(struct amdgpu_ip_block
> > *ip_block)> 
> >   	/* initialize ih control register offset */
> >   	ih_v7_0_init_register_offset(adev);
> > 
> > -	sw_ring_size = (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == 
IP_VERSION(7,
> > 1, 0)) ? -			IH_SW_RING_SIZE : PAGE_SIZE;
> > -	r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, sw_ring_size, 
true);
> > +	r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE,
> > true);
> > 
> >   	if (r)
> >   	
> >   		return r;
> 
> Looks plausible to me.
> 
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> 
> The only other which uses PAGE_SIZE for the soft IH ring is ih_v6_1.c so
> maybe that one needs tweaking too?

I can tweak that too for sure.

As a side note, though, IH 6.1 is used by RDNA 3.5 APUs which need further 
work to make use of retry faults because the APUs don't have the retry CAM so 
we'll need to come up with a different way to filter the interrupts in software 
as we already discussed in a thread on the previous series. Same goes for 
RDNA1-2 dGPUs which also don't seem to have the retry CAM.

Thanks & best regards,
Timur