diff for duplicates of <586DBD68.7090509@hisilicon.com> diff --git a/a/1.txt b/N1/1.txt index dacac50..bfac6da 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -16,7 +16,7 @@ On 2016/12/26 17:36, Chen Feng wrote: > > Tested on HiKey960 Board. > -> Signed-off-by: Chen Feng <puck.chen@hisilicon.com> +> Signed-off-by: Chen Feng <puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> > --- > arch/arm64/boot/dts/hisilicon/Makefile | 1 + > arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 34 +++++ @@ -64,13 +64,13 @@ On 2016/12/26 17:36, Chen Feng wrote: > + stdout-path = "serial5:115200n8"; > + }; > + -> + memory at 0 { +> + memory@0 { > + device_type = "memory"; > + reg = <0x0 0x00400000 0x0 0xBFE00000>; > + }; > + > + soc { -> + uart5: uart at fdf05000 { +> + uart5: uart@fdf05000 { > + status = "ok"; > + }; > + }; @@ -135,56 +135,56 @@ On 2016/12/26 17:36, Chen Feng wrote: > + }; > + }; > + -> + cpu0: cpu at 0 { +> + cpu0: cpu@0 { > + compatible = "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + }; > + -> + cpu1: cpu at 1 { +> + cpu1: cpu@1 { > + compatible = "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x1>; > + enable-method = "psci"; > + }; > + -> + cpu2: cpu at 2 { +> + cpu2: cpu@2 { > + compatible = "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x2>; > + enable-method = "psci"; > + }; > + -> + cpu3: cpu at 3 { +> + cpu3: cpu@3 { > + compatible = "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x3>; > + enable-method = "psci"; > + }; > + -> + cpu4: cpu at 100 { +> + cpu4: cpu@100 { > + compatible = "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x100>; > + enable-method = "psci"; > + }; > + -> + cpu5: cpu at 101 { +> + cpu5: cpu@101 { > + compatible = "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x101>; > + enable-method = "psci"; > + }; > + -> + cpu6: cpu at 102 { +> + cpu6: cpu@102 { > + compatible = "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x102>; > + enable-method = "psci"; > + }; > + -> + cpu7: cpu at 103 { +> + cpu7: cpu@103 { > + compatible = "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x103>; @@ -192,7 +192,7 @@ On 2016/12/26 17:36, Chen Feng wrote: > + }; > + }; > + -> + gic: interrupt-controller at e82b0000 { +> + gic: interrupt-controller@e82b0000 { > + compatible = "arm,gic-400"; > + reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ > + <0x0 0xe82b2000 0 0x2000>, /* GICC */ @@ -227,7 +227,7 @@ On 2016/12/26 17:36, Chen Feng wrote: > + clock-output-names = "fixed:uart5"; > + }; > + -> + uart5: uart at fdf05000 { +> + uart5: uart@fdf05000 { > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0x0 0xfdf05000 0x0 0x1000>; > + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; @@ -237,4 +237,9 @@ On 2016/12/26 17:36, Chen Feng wrote: > + }; > + }; > +}; -> +> + +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index e131d9a..2f66a97 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,9 +1,19 @@ "ref\01482744972-56622-1-git-send-email-puck.chen@hisilicon.com\0" "ref\01482744972-56622-2-git-send-email-puck.chen@hisilicon.com\0" - "From\0puck.chen@hisilicon.com (Chen Feng)\0" - "Subject\0[RESEND 2/2] arm64: dts: Add dts files for Hisilicon Hi3660 SoC\0" + "ref\01482744972-56622-2-git-send-email-puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org\0" + "From\0Chen Feng <puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>\0" + "Subject\0Re: [RESEND 2/2] arm64: dts: Add dts files for Hisilicon Hi3660 SoC\0" "Date\0Thu, 5 Jan 2017 11:28:40 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0xuwei5-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org" + robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org + mark.rutland-5wv7dgnIgG8@public.gmane.org + catalin.marinas-5wv7dgnIgG8@public.gmane.org + will.deacon-5wv7dgnIgG8@public.gmane.org + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" + "Cc\0suzhuangluan-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org" + " xuyiping-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org\0" "\00:1\0" "b\0" "Hi will&catalin,\n" @@ -24,7 +34,7 @@ "> \n" "> Tested on HiKey960 Board.\n" "> \n" - "> Signed-off-by: Chen Feng <puck.chen@hisilicon.com>\n" + "> Signed-off-by: Chen Feng <puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>\n" "> ---\n" "> arch/arm64/boot/dts/hisilicon/Makefile | 1 +\n" "> arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 34 +++++\n" @@ -72,13 +82,13 @@ "> +\t\tstdout-path = \"serial5:115200n8\";\n" "> +\t};\n" "> +\n" - "> +\tmemory at 0 {\n" + "> +\tmemory@0 {\n" "> +\t\tdevice_type = \"memory\";\n" "> +\t\treg = <0x0 0x00400000 0x0 0xBFE00000>;\n" "> +\t};\n" "> +\n" "> +\tsoc {\n" - "> +\t\tuart5: uart at fdf05000 {\n" + "> +\t\tuart5: uart@fdf05000 {\n" "> +\t\t\tstatus = \"ok\";\n" "> +\t\t};\n" "> +\t};\n" @@ -143,56 +153,56 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu0: cpu at 0 {\n" + "> +\t\tcpu0: cpu@0 {\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x0>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu1: cpu at 1 {\n" + "> +\t\tcpu1: cpu@1 {\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x1>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu2: cpu at 2 {\n" + "> +\t\tcpu2: cpu@2 {\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x2>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu3: cpu at 3 {\n" + "> +\t\tcpu3: cpu@3 {\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x3>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu4: cpu at 100 {\n" + "> +\t\tcpu4: cpu@100 {\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x100>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu5: cpu at 101 {\n" + "> +\t\tcpu5: cpu@101 {\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x101>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu6: cpu at 102 {\n" + "> +\t\tcpu6: cpu@102 {\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x102>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu7: cpu at 103 {\n" + "> +\t\tcpu7: cpu@103 {\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x103>;\n" @@ -200,7 +210,7 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller at e82b0000 {\n" + "> +\tgic: interrupt-controller@e82b0000 {\n" "> +\t\tcompatible = \"arm,gic-400\";\n" "> +\t\treg = <0x0 0xe82b1000 0 0x1000>, /* GICD */\n" "> +\t\t <0x0 0xe82b2000 0 0x2000>, /* GICC */\n" @@ -235,7 +245,7 @@ "> +\t\t\tclock-output-names = \"fixed:uart5\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart5: uart at fdf05000 {\n" + "> +\t\tuart5: uart@fdf05000 {\n" "> +\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "> +\t\t\treg = <0x0 0xfdf05000 0x0 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -245,6 +255,11 @@ "> +\t\t};\n" "> +\t};\n" "> +};\n" - > + "> \n" + "\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -b74d51dba7ef51d447d98d8d2acabe3e9db54cf828388fe64c37d32a8033f847 +2bd0e7c687947b6eb791fc89f7341201ec2c9358c3fd97030daa69559d94778f
diff --git a/a/1.txt b/N2/1.txt index dacac50..c8e2f17 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -64,13 +64,13 @@ On 2016/12/26 17:36, Chen Feng wrote: > + stdout-path = "serial5:115200n8"; > + }; > + -> + memory at 0 { +> + memory@0 { > + device_type = "memory"; > + reg = <0x0 0x00400000 0x0 0xBFE00000>; > + }; > + > + soc { -> + uart5: uart at fdf05000 { +> + uart5: uart@fdf05000 { > + status = "ok"; > + }; > + }; @@ -135,56 +135,56 @@ On 2016/12/26 17:36, Chen Feng wrote: > + }; > + }; > + -> + cpu0: cpu at 0 { +> + cpu0: cpu@0 { > + compatible = "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + }; > + -> + cpu1: cpu at 1 { +> + cpu1: cpu@1 { > + compatible = "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x1>; > + enable-method = "psci"; > + }; > + -> + cpu2: cpu at 2 { +> + cpu2: cpu@2 { > + compatible = "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x2>; > + enable-method = "psci"; > + }; > + -> + cpu3: cpu at 3 { +> + cpu3: cpu@3 { > + compatible = "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x3>; > + enable-method = "psci"; > + }; > + -> + cpu4: cpu at 100 { +> + cpu4: cpu@100 { > + compatible = "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x100>; > + enable-method = "psci"; > + }; > + -> + cpu5: cpu at 101 { +> + cpu5: cpu@101 { > + compatible = "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x101>; > + enable-method = "psci"; > + }; > + -> + cpu6: cpu at 102 { +> + cpu6: cpu@102 { > + compatible = "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x102>; > + enable-method = "psci"; > + }; > + -> + cpu7: cpu at 103 { +> + cpu7: cpu@103 { > + compatible = "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x103>; @@ -192,7 +192,7 @@ On 2016/12/26 17:36, Chen Feng wrote: > + }; > + }; > + -> + gic: interrupt-controller at e82b0000 { +> + gic: interrupt-controller@e82b0000 { > + compatible = "arm,gic-400"; > + reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ > + <0x0 0xe82b2000 0 0x2000>, /* GICC */ @@ -227,7 +227,7 @@ On 2016/12/26 17:36, Chen Feng wrote: > + clock-output-names = "fixed:uart5"; > + }; > + -> + uart5: uart at fdf05000 { +> + uart5: uart@fdf05000 { > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0x0 0xfdf05000 0x0 0x1000>; > + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; diff --git a/a/content_digest b/N2/content_digest index e131d9a..e31e227 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,9 +1,18 @@ "ref\01482744972-56622-1-git-send-email-puck.chen@hisilicon.com\0" "ref\01482744972-56622-2-git-send-email-puck.chen@hisilicon.com\0" - "From\0puck.chen@hisilicon.com (Chen Feng)\0" - "Subject\0[RESEND 2/2] arm64: dts: Add dts files for Hisilicon Hi3660 SoC\0" + "From\0Chen Feng <puck.chen@hisilicon.com>\0" + "Subject\0Re: [RESEND 2/2] arm64: dts: Add dts files for Hisilicon Hi3660 SoC\0" "Date\0Thu, 5 Jan 2017 11:28:40 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0<xuwei5@hisilicon.com>" + <robh+dt@kernel.org> + <mark.rutland@arm.com> + <catalin.marinas@arm.com> + <will.deacon@arm.com> + <linux-arm-kernel@lists.infradead.org> + <devicetree@vger.kernel.org> + " <linux-kernel@vger.kernel.org>\0" + "Cc\0<suzhuangluan@hisilicon.com>" + " <xuyiping@hisilicon.com>\0" "\00:1\0" "b\0" "Hi will&catalin,\n" @@ -72,13 +81,13 @@ "> +\t\tstdout-path = \"serial5:115200n8\";\n" "> +\t};\n" "> +\n" - "> +\tmemory at 0 {\n" + "> +\tmemory@0 {\n" "> +\t\tdevice_type = \"memory\";\n" "> +\t\treg = <0x0 0x00400000 0x0 0xBFE00000>;\n" "> +\t};\n" "> +\n" "> +\tsoc {\n" - "> +\t\tuart5: uart at fdf05000 {\n" + "> +\t\tuart5: uart@fdf05000 {\n" "> +\t\t\tstatus = \"ok\";\n" "> +\t\t};\n" "> +\t};\n" @@ -143,56 +152,56 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu0: cpu at 0 {\n" + "> +\t\tcpu0: cpu@0 {\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x0>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu1: cpu at 1 {\n" + "> +\t\tcpu1: cpu@1 {\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x1>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu2: cpu at 2 {\n" + "> +\t\tcpu2: cpu@2 {\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x2>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu3: cpu at 3 {\n" + "> +\t\tcpu3: cpu@3 {\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x3>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu4: cpu at 100 {\n" + "> +\t\tcpu4: cpu@100 {\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x100>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu5: cpu at 101 {\n" + "> +\t\tcpu5: cpu@101 {\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x101>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu6: cpu at 102 {\n" + "> +\t\tcpu6: cpu@102 {\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x102>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu7: cpu at 103 {\n" + "> +\t\tcpu7: cpu@103 {\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x103>;\n" @@ -200,7 +209,7 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller at e82b0000 {\n" + "> +\tgic: interrupt-controller@e82b0000 {\n" "> +\t\tcompatible = \"arm,gic-400\";\n" "> +\t\treg = <0x0 0xe82b1000 0 0x1000>, /* GICD */\n" "> +\t\t <0x0 0xe82b2000 0 0x2000>, /* GICC */\n" @@ -235,7 +244,7 @@ "> +\t\t\tclock-output-names = \"fixed:uart5\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart5: uart at fdf05000 {\n" + "> +\t\tuart5: uart@fdf05000 {\n" "> +\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "> +\t\t\treg = <0x0 0xfdf05000 0x0 0x1000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -247,4 +256,4 @@ "> +};\n" > -b74d51dba7ef51d447d98d8d2acabe3e9db54cf828388fe64c37d32a8033f847 +2169374a051ce0b3192cd89d542e0f47e7dc4adcde5f281e3fdab2ce2ebab673
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.