From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Zhong Subject: Re: [PATCH v2 03/26] drm/rockchip: dw-mipi-dsi: pass mode in where needed Date: Sun, 22 Jan 2017 12:00:22 +0800 Message-ID: <58842E56.2000405@rock-chips.com> References: <20170121163128.22240-1-john@metanate.com> <20170121163128.22240-4-john@metanate.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20170121163128.22240-4-john@metanate.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: John Keeping , Mark Yao Cc: linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org List-Id: linux-rockchip.vger.kernel.org SGkgSm9obgoKUmV2aWV3ZWQtYnk6IENocmlzIFpob25nIDx6eXdAcm9jay1jaGlwcy5jb20+CgpP biAwMS8yMi8yMDE3IDEyOjMxIEFNLCBKb2huIEtlZXBpbmcgd3JvdGU6Cj4gVGhpcyBzaG93cyB0 aGF0IHdlIG9ubHkgdXNlIHRoZSBtb2RlIGZyb20gdGhlIGVuYWJsZSBmdW5jdGlvbiBhbmQKPiBw cmVwYXJlcyB1cyB0byByZW1vdmUgdGhlICJtb2RlIiBmaWVsZCBhbmQgdGhlIG1vZGVfc2V0IGhv b2sgaW4gdGhlIG5leHQKPiBjb21taXQuCj4KPiBTaWduZWQtb2ZmLWJ5OiBKb2huIEtlZXBpbmcg PGpvaG5AbWV0YW5hdGUuY29tPgo+IC0tLQo+IE5ldyBpbiB2Mgo+IC0tLQo+ICAgZHJpdmVycy9n cHUvZHJtL3JvY2tjaGlwL2R3LW1pcGktZHNpLmMgfCA0MSArKysrKysrKysrKysrKysrKystLS0t LS0tLS0tLS0tLS0tCj4gICAxIGZpbGUgY2hhbmdlZCwgMjIgaW5zZXJ0aW9ucygrKSwgMTkgZGVs ZXRpb25zKC0pCj4KPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL2R3LW1p cGktZHNpLmMgYi9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvZHctbWlwaS1kc2kuYwo+IGluZGV4 IGJiZDk5MjI5OWY3My4uY2RiZDI1MDg3ZTgzIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvZ3B1L2Ry bS9yb2NrY2hpcC9kdy1taXBpLWRzaS5jCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlw L2R3LW1pcGktZHNpLmMKPiBAQCAtMzMwLDExICszMzAsMTEgQEAgc3RhdGljIGludCBtYXhfbWJw c190b190ZXN0ZGluKHVuc2lnbmVkIGludCBtYXhfbWJwcykKPiAgICAqIFRoZSBjb250cm9sbGVy IHNob3VsZCBnZW5lcmF0ZSAyIGZyYW1lcyBiZWZvcmUKPiAgICAqIHByZXBhcmluZyB0aGUgcGVy aXBoZXJhbC4KPiAgICAqLwo+IC1zdGF0aWMgdm9pZCBkd19taXBpX2RzaV93YWl0X2Zvcl90d29f ZnJhbWVzKHN0cnVjdCBkd19taXBpX2RzaSAqZHNpKQo+ICtzdGF0aWMgdm9pZCBkd19taXBpX2Rz aV93YWl0X2Zvcl90d29fZnJhbWVzKHN0cnVjdCBkcm1fZGlzcGxheV9tb2RlICptb2RlKQo+ICAg ewo+ICAgCWludCByZWZyZXNoLCB0d29fZnJhbWVzOwo+ICAgCj4gLQlyZWZyZXNoID0gZHJtX21v ZGVfdnJlZnJlc2goZHNpLT5tb2RlKTsKPiArCXJlZnJlc2ggPSBkcm1fbW9kZV92cmVmcmVzaCht b2RlKTsKPiAgIAl0d29fZnJhbWVzID0gRElWX1JPVU5EX1VQKE1TRUNfUEVSX1NFQywgcmVmcmVz aCkgKiAyOwo+ICAgCW1zbGVlcCh0d29fZnJhbWVzKTsKPiAgIH0KPiBAQCAtNDU5LDcgKzQ1OSw4 IEBAIHN0YXRpYyBpbnQgZHdfbWlwaV9kc2lfcGh5X2luaXQoc3RydWN0IGR3X21pcGlfZHNpICpk c2kpCj4gICAJcmV0dXJuIHJldDsKPiAgIH0KPiAgIAo+IC1zdGF0aWMgaW50IGR3X21pcGlfZHNp X2dldF9sYW5lX2JwcyhzdHJ1Y3QgZHdfbWlwaV9kc2kgKmRzaSkKPiArc3RhdGljIGludCBkd19t aXBpX2RzaV9nZXRfbGFuZV9icHMoc3RydWN0IGR3X21pcGlfZHNpICpkc2ksCj4gKwkJCQkgICAg c3RydWN0IGRybV9kaXNwbGF5X21vZGUgKm1vZGUpCj4gICB7Cj4gICAJdW5zaWduZWQgaW50IGks IHByZTsKPiAgIAl1bnNpZ25lZCBsb25nIG1wY2xrLCBwbGxyZWYsIHRtcDsKPiBAQCAtNDc0LDcg KzQ3NSw3IEBAIHN0YXRpYyBpbnQgZHdfbWlwaV9kc2lfZ2V0X2xhbmVfYnBzKHN0cnVjdCBkd19t aXBpX2RzaSAqZHNpKQo+ICAgCQlyZXR1cm4gYnBwOwo+ICAgCX0KPiAgIAo+IC0JbXBjbGsgPSBE SVZfUk9VTkRfVVAoZHNpLT5tb2RlLT5jbG9jaywgTVNFQ19QRVJfU0VDKTsKPiArCW1wY2xrID0g RElWX1JPVU5EX1VQKG1vZGUtPmNsb2NrLCBNU0VDX1BFUl9TRUMpOwo+ICAgCWlmIChtcGNsaykg ewo+ICAgCQkvKiB0YWtlIDEgLyAwLjksIHNpbmNlIG1icHMgbXVzdCBiaWcgdGhhbiBiYW5kd2lk dGggb2YgUkdCICovCj4gICAJCXRtcCA9IG1wY2xrICogKGJwcCAvIGRzaS0+bGFuZXMpICogMTAg LyA5Owo+IEBAIC03NDIsNDMgKzc0Myw0NCBAQCBzdGF0aWMgdm9pZCBkd19taXBpX2RzaV9jb21t YW5kX21vZGVfY29uZmlnKHN0cnVjdCBkd19taXBpX2RzaSAqZHNpKQo+ICAgCj4gICAvKiBHZXQg bGFuZSBieXRlIGNsb2NrIGN5Y2xlcy4gKi8KPiAgIHN0YXRpYyB1MzIgZHdfbWlwaV9kc2lfZ2V0 X2hjb21wb25lbnRfbGJjYyhzdHJ1Y3QgZHdfbWlwaV9kc2kgKmRzaSwKPiArCQkJCQkgICBzdHJ1 Y3QgZHJtX2Rpc3BsYXlfbW9kZSAqbW9kZSwKPiAgIAkJCQkJICAgdTMyIGhjb21wb25lbnQpCj4g ICB7Cj4gICAJdTMyIGZyYWMsIGxiY2M7Cj4gICAKPiAgIAlsYmNjID0gaGNvbXBvbmVudCAqIGRz aS0+bGFuZV9tYnBzICogTVNFQ19QRVJfU0VDIC8gODsKPiAgIAo+IC0JZnJhYyA9IGxiY2MgJSBk c2ktPm1vZGUtPmNsb2NrOwo+IC0JbGJjYyA9IGxiY2MgLyBkc2ktPm1vZGUtPmNsb2NrOwo+ICsJ ZnJhYyA9IGxiY2MgJSBtb2RlLT5jbG9jazsKPiArCWxiY2MgPSBsYmNjIC8gbW9kZS0+Y2xvY2s7 Cj4gICAJaWYgKGZyYWMpCj4gICAJCWxiY2MrKzsKPiAgIAo+ICAgCXJldHVybiBsYmNjOwo+ICAg fQo+ICAgCj4gLXN0YXRpYyB2b2lkIGR3X21pcGlfZHNpX2xpbmVfdGltZXJfY29uZmlnKHN0cnVj dCBkd19taXBpX2RzaSAqZHNpKQo+ICtzdGF0aWMgdm9pZCBkd19taXBpX2RzaV9saW5lX3RpbWVy X2NvbmZpZyhzdHJ1Y3QgZHdfbWlwaV9kc2kgKmRzaSwKPiArCQkJCQkgIHN0cnVjdCBkcm1fZGlz cGxheV9tb2RlICptb2RlKQo+ICAgewo+ICAgCXUzMiBodG90YWwsIGhzYSwgaGJwLCBsYmNjOwo+ IC0Jc3RydWN0IGRybV9kaXNwbGF5X21vZGUgKm1vZGUgPSBkc2ktPm1vZGU7Cj4gICAKPiAgIAlo dG90YWwgPSBtb2RlLT5odG90YWw7Cj4gICAJaHNhID0gbW9kZS0+aHN5bmNfZW5kIC0gbW9kZS0+ aHN5bmNfc3RhcnQ7Cj4gICAJaGJwID0gbW9kZS0+aHRvdGFsIC0gbW9kZS0+aHN5bmNfZW5kOwo+ ICAgCj4gLQlsYmNjID0gZHdfbWlwaV9kc2lfZ2V0X2hjb21wb25lbnRfbGJjYyhkc2ksIGh0b3Rh bCk7Cj4gKwlsYmNjID0gZHdfbWlwaV9kc2lfZ2V0X2hjb21wb25lbnRfbGJjYyhkc2ksIG1vZGUs IGh0b3RhbCk7Cj4gICAJZHNpX3dyaXRlKGRzaSwgRFNJX1ZJRF9ITElORV9USU1FLCBsYmNjKTsK PiAgIAo+IC0JbGJjYyA9IGR3X21pcGlfZHNpX2dldF9oY29tcG9uZW50X2xiY2MoZHNpLCBoc2Ep Owo+ICsJbGJjYyA9IGR3X21pcGlfZHNpX2dldF9oY29tcG9uZW50X2xiY2MoZHNpLCBtb2RlLCBo c2EpOwo+ICAgCWRzaV93cml0ZShkc2ksIERTSV9WSURfSFNBX1RJTUUsIGxiY2MpOwo+ICAgCj4g LQlsYmNjID0gZHdfbWlwaV9kc2lfZ2V0X2hjb21wb25lbnRfbGJjYyhkc2ksIGhicCk7Cj4gKwls YmNjID0gZHdfbWlwaV9kc2lfZ2V0X2hjb21wb25lbnRfbGJjYyhkc2ksIG1vZGUsIGhicCk7Cj4g ICAJZHNpX3dyaXRlKGRzaSwgRFNJX1ZJRF9IQlBfVElNRSwgbGJjYyk7Cj4gICB9Cj4gICAKPiAt c3RhdGljIHZvaWQgZHdfbWlwaV9kc2lfdmVydGljYWxfdGltaW5nX2NvbmZpZyhzdHJ1Y3QgZHdf bWlwaV9kc2kgKmRzaSkKPiArc3RhdGljIHZvaWQgZHdfbWlwaV9kc2lfdmVydGljYWxfdGltaW5n X2NvbmZpZyhzdHJ1Y3QgZHdfbWlwaV9kc2kgKmRzaSwKPiArCQkJCQkgICAgICAgc3RydWN0IGRy bV9kaXNwbGF5X21vZGUgKm1vZGUpCj4gICB7Cj4gICAJdTMyIHZhY3RpdmUsIHZzYSwgdmZwLCB2 YnA7Cj4gLQlzdHJ1Y3QgZHJtX2Rpc3BsYXlfbW9kZSAqbW9kZSA9IGRzaS0+bW9kZTsKPiAgIAo+ ICAgCXZhY3RpdmUgPSBtb2RlLT52ZGlzcGxheTsKPiAgIAl2c2EgPSBtb2RlLT52c3luY19lbmQg LSBtb2RlLT52c3luY19zdGFydDsKPiBAQCAtODUyLDExICs4NTQsMTIgQEAgc3RhdGljIHZvaWQg ZHdfbWlwaV9kc2lfZW5jb2Rlcl9kaXNhYmxlKHN0cnVjdCBkcm1fZW5jb2RlciAqZW5jb2RlcikK PiAgIHN0YXRpYyB2b2lkIGR3X21pcGlfZHNpX2VuY29kZXJfZW5hYmxlKHN0cnVjdCBkcm1fZW5j b2RlciAqZW5jb2RlcikKPiAgIHsKPiAgIAlzdHJ1Y3QgZHdfbWlwaV9kc2kgKmRzaSA9IGVuY29k ZXJfdG9fZHNpKGVuY29kZXIpOwo+ICsJc3RydWN0IGRybV9kaXNwbGF5X21vZGUgKm1vZGUgPSBk c2ktPm1vZGU7Cj4gICAJaW50IG11eCA9IGRybV9vZl9lbmNvZGVyX2FjdGl2ZV9lbmRwb2ludF9p ZChkc2ktPmRldi0+b2Zfbm9kZSwgZW5jb2Rlcik7Cj4gICAJdTMyIHZhbDsKPiAgIAlpbnQgcmV0 Owo+ICAgCj4gLQlyZXQgPSBkd19taXBpX2RzaV9nZXRfbGFuZV9icHMoZHNpKTsKPiArCXJldCA9 IGR3X21pcGlfZHNpX2dldF9sYW5lX2Jwcyhkc2ksIG1vZGUpOwo+ICAgCWlmIChyZXQgPCAwKQo+ ICAgCQlyZXR1cm47Cj4gICAKPiBAQCAtODY2LDEzICs4NjksMTMgQEAgc3RhdGljIHZvaWQgZHdf bWlwaV9kc2lfZW5jb2Rlcl9lbmFibGUoc3RydWN0IGRybV9lbmNvZGVyICplbmNvZGVyKQo+ICAg CX0KPiAgIAo+ICAgCWR3X21pcGlfZHNpX2luaXQoZHNpKTsKPiAtCWR3X21pcGlfZHNpX2RwaV9j b25maWcoZHNpLCBkc2ktPm1vZGUpOwo+ICsJZHdfbWlwaV9kc2lfZHBpX2NvbmZpZyhkc2ksIG1v ZGUpOwo+ICAgCWR3X21pcGlfZHNpX3BhY2tldF9oYW5kbGVyX2NvbmZpZyhkc2kpOwo+ICAgCWR3 X21pcGlfZHNpX3ZpZGVvX21vZGVfY29uZmlnKGRzaSk7Cj4gLQlkd19taXBpX2RzaV92aWRlb19w YWNrZXRfY29uZmlnKGRzaSwgZHNpLT5tb2RlKTsKPiArCWR3X21pcGlfZHNpX3ZpZGVvX3BhY2tl dF9jb25maWcoZHNpLCBtb2RlKTsKPiAgIAlkd19taXBpX2RzaV9jb21tYW5kX21vZGVfY29uZmln KGRzaSk7Cj4gLQlkd19taXBpX2RzaV9saW5lX3RpbWVyX2NvbmZpZyhkc2kpOwo+IC0JZHdfbWlw aV9kc2lfdmVydGljYWxfdGltaW5nX2NvbmZpZyhkc2kpOwo+ICsJZHdfbWlwaV9kc2lfbGluZV90 aW1lcl9jb25maWcoZHNpLCBtb2RlKTsKPiArCWR3X21pcGlfZHNpX3ZlcnRpY2FsX3RpbWluZ19j b25maWcoZHNpLCBtb2RlKTsKPiAgIAlkd19taXBpX2RzaV9kcGh5X3RpbWluZ19jb25maWcoZHNp KTsKPiAgIAlkd19taXBpX2RzaV9kcGh5X2ludGVyZmFjZV9jb25maWcoZHNpKTsKPiAgIAlkd19t aXBpX2RzaV9jbGVhcl9lcnIoZHNpKTsKPiBAQCAtODgwLDcgKzg4Myw3IEBAIHN0YXRpYyB2b2lk IGR3X21pcGlfZHNpX2VuY29kZXJfZW5hYmxlKHN0cnVjdCBkcm1fZW5jb2RlciAqZW5jb2RlcikK PiAgIAkJZGV2X2Vycihkc2ktPmRldiwgImZhaWxlZCB0byBwcmVwYXJlIHBhbmVsXG4iKTsKPiAg IAo+ICAgCWR3X21pcGlfZHNpX3BoeV9pbml0KGRzaSk7Cj4gLQlkd19taXBpX2RzaV93YWl0X2Zv cl90d29fZnJhbWVzKGRzaSk7Cj4gKwlkd19taXBpX2RzaV93YWl0X2Zvcl90d29fZnJhbWVzKG1v ZGUpOwo+ICAgCj4gICAJZHdfbWlwaV9kc2lfc2V0X21vZGUoZHNpLCBEV19NSVBJX0RTSV9WSURf TU9ERSk7Cj4gICAJZHJtX3BhbmVsX2VuYWJsZShkc2ktPnBhbmVsKTsKCgpfX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0 CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3Rv cC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 From: zyw@rock-chips.com (Chris Zhong) Date: Sun, 22 Jan 2017 12:00:22 +0800 Subject: [PATCH v2 03/26] drm/rockchip: dw-mipi-dsi: pass mode in where needed In-Reply-To: <20170121163128.22240-4-john@metanate.com> References: <20170121163128.22240-1-john@metanate.com> <20170121163128.22240-4-john@metanate.com> Message-ID: <58842E56.2000405@rock-chips.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi John Reviewed-by: Chris Zhong On 01/22/2017 12:31 AM, John Keeping wrote: > This shows that we only use the mode from the enable function and > prepares us to remove the "mode" field and the mode_set hook in the next > commit. > > Signed-off-by: John Keeping > --- > New in v2 > --- > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 41 ++++++++++++++++++---------------- > 1 file changed, 22 insertions(+), 19 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > index bbd992299f73..cdbd25087e83 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > @@ -330,11 +330,11 @@ static int max_mbps_to_testdin(unsigned int max_mbps) > * The controller should generate 2 frames before > * preparing the peripheral. > */ > -static void dw_mipi_dsi_wait_for_two_frames(struct dw_mipi_dsi *dsi) > +static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode *mode) > { > int refresh, two_frames; > > - refresh = drm_mode_vrefresh(dsi->mode); > + refresh = drm_mode_vrefresh(mode); > two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2; > msleep(two_frames); > } > @@ -459,7 +459,8 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) > return ret; > } > > -static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi) > +static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi, > + struct drm_display_mode *mode) > { > unsigned int i, pre; > unsigned long mpclk, pllref, tmp; > @@ -474,7 +475,7 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi) > return bpp; > } > > - mpclk = DIV_ROUND_UP(dsi->mode->clock, MSEC_PER_SEC); > + mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); > if (mpclk) { > /* take 1 / 0.9, since mbps must big than bandwidth of RGB */ > tmp = mpclk * (bpp / dsi->lanes) * 10 / 9; > @@ -742,43 +743,44 @@ static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) > > /* Get lane byte clock cycles. */ > static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, > + struct drm_display_mode *mode, > u32 hcomponent) > { > u32 frac, lbcc; > > lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8; > > - frac = lbcc % dsi->mode->clock; > - lbcc = lbcc / dsi->mode->clock; > + frac = lbcc % mode->clock; > + lbcc = lbcc / mode->clock; > if (frac) > lbcc++; > > return lbcc; > } > > -static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi) > +static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi, > + struct drm_display_mode *mode) > { > u32 htotal, hsa, hbp, lbcc; > - struct drm_display_mode *mode = dsi->mode; > > htotal = mode->htotal; > hsa = mode->hsync_end - mode->hsync_start; > hbp = mode->htotal - mode->hsync_end; > > - lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal); > + lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal); > dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); > > - lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa); > + lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa); > dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); > > - lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp); > + lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp); > dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); > } > > -static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi) > +static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi, > + struct drm_display_mode *mode) > { > u32 vactive, vsa, vfp, vbp; > - struct drm_display_mode *mode = dsi->mode; > > vactive = mode->vdisplay; > vsa = mode->vsync_end - mode->vsync_start; > @@ -852,11 +854,12 @@ static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder) > static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) > { > struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder); > + struct drm_display_mode *mode = dsi->mode; > int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder); > u32 val; > int ret; > > - ret = dw_mipi_dsi_get_lane_bps(dsi); > + ret = dw_mipi_dsi_get_lane_bps(dsi, mode); > if (ret < 0) > return; > > @@ -866,13 +869,13 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) > } > > dw_mipi_dsi_init(dsi); > - dw_mipi_dsi_dpi_config(dsi, dsi->mode); > + dw_mipi_dsi_dpi_config(dsi, mode); > dw_mipi_dsi_packet_handler_config(dsi); > dw_mipi_dsi_video_mode_config(dsi); > - dw_mipi_dsi_video_packet_config(dsi, dsi->mode); > + dw_mipi_dsi_video_packet_config(dsi, mode); > dw_mipi_dsi_command_mode_config(dsi); > - dw_mipi_dsi_line_timer_config(dsi); > - dw_mipi_dsi_vertical_timing_config(dsi); > + dw_mipi_dsi_line_timer_config(dsi, mode); > + dw_mipi_dsi_vertical_timing_config(dsi, mode); > dw_mipi_dsi_dphy_timing_config(dsi); > dw_mipi_dsi_dphy_interface_config(dsi); > dw_mipi_dsi_clear_err(dsi); > @@ -880,7 +883,7 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) > dev_err(dsi->dev, "failed to prepare panel\n"); > > dw_mipi_dsi_phy_init(dsi); > - dw_mipi_dsi_wait_for_two_frames(dsi); > + dw_mipi_dsi_wait_for_two_frames(mode); > > dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE); > drm_panel_enable(dsi->panel); From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751230AbdAVEAe (ORCPT ); Sat, 21 Jan 2017 23:00:34 -0500 Received: from regular1.263xmail.com ([211.150.99.131]:57734 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750905AbdAVEA3 (ORCPT ); Sat, 21 Jan 2017 23:00:29 -0500 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-RL-SENDER: zyw@rock-chips.com X-FST-TO: linux-kernel@vger.kernel.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: zyw@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH v2 03/26] drm/rockchip: dw-mipi-dsi: pass mode in where needed To: John Keeping , Mark Yao References: <20170121163128.22240-1-john@metanate.com> <20170121163128.22240-4-john@metanate.com> Cc: dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org From: Chris Zhong Message-ID: <58842E56.2000405@rock-chips.com> Date: Sun, 22 Jan 2017 12:00:22 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-Version: 1.0 In-Reply-To: <20170121163128.22240-4-john@metanate.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi John Reviewed-by: Chris Zhong On 01/22/2017 12:31 AM, John Keeping wrote: > This shows that we only use the mode from the enable function and > prepares us to remove the "mode" field and the mode_set hook in the next > commit. > > Signed-off-by: John Keeping > --- > New in v2 > --- > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 41 ++++++++++++++++++---------------- > 1 file changed, 22 insertions(+), 19 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > index bbd992299f73..cdbd25087e83 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > @@ -330,11 +330,11 @@ static int max_mbps_to_testdin(unsigned int max_mbps) > * The controller should generate 2 frames before > * preparing the peripheral. > */ > -static void dw_mipi_dsi_wait_for_two_frames(struct dw_mipi_dsi *dsi) > +static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode *mode) > { > int refresh, two_frames; > > - refresh = drm_mode_vrefresh(dsi->mode); > + refresh = drm_mode_vrefresh(mode); > two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2; > msleep(two_frames); > } > @@ -459,7 +459,8 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) > return ret; > } > > -static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi) > +static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi, > + struct drm_display_mode *mode) > { > unsigned int i, pre; > unsigned long mpclk, pllref, tmp; > @@ -474,7 +475,7 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi) > return bpp; > } > > - mpclk = DIV_ROUND_UP(dsi->mode->clock, MSEC_PER_SEC); > + mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); > if (mpclk) { > /* take 1 / 0.9, since mbps must big than bandwidth of RGB */ > tmp = mpclk * (bpp / dsi->lanes) * 10 / 9; > @@ -742,43 +743,44 @@ static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) > > /* Get lane byte clock cycles. */ > static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, > + struct drm_display_mode *mode, > u32 hcomponent) > { > u32 frac, lbcc; > > lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8; > > - frac = lbcc % dsi->mode->clock; > - lbcc = lbcc / dsi->mode->clock; > + frac = lbcc % mode->clock; > + lbcc = lbcc / mode->clock; > if (frac) > lbcc++; > > return lbcc; > } > > -static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi) > +static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi, > + struct drm_display_mode *mode) > { > u32 htotal, hsa, hbp, lbcc; > - struct drm_display_mode *mode = dsi->mode; > > htotal = mode->htotal; > hsa = mode->hsync_end - mode->hsync_start; > hbp = mode->htotal - mode->hsync_end; > > - lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal); > + lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal); > dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); > > - lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa); > + lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa); > dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); > > - lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp); > + lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp); > dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); > } > > -static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi) > +static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi, > + struct drm_display_mode *mode) > { > u32 vactive, vsa, vfp, vbp; > - struct drm_display_mode *mode = dsi->mode; > > vactive = mode->vdisplay; > vsa = mode->vsync_end - mode->vsync_start; > @@ -852,11 +854,12 @@ static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder) > static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) > { > struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder); > + struct drm_display_mode *mode = dsi->mode; > int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder); > u32 val; > int ret; > > - ret = dw_mipi_dsi_get_lane_bps(dsi); > + ret = dw_mipi_dsi_get_lane_bps(dsi, mode); > if (ret < 0) > return; > > @@ -866,13 +869,13 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) > } > > dw_mipi_dsi_init(dsi); > - dw_mipi_dsi_dpi_config(dsi, dsi->mode); > + dw_mipi_dsi_dpi_config(dsi, mode); > dw_mipi_dsi_packet_handler_config(dsi); > dw_mipi_dsi_video_mode_config(dsi); > - dw_mipi_dsi_video_packet_config(dsi, dsi->mode); > + dw_mipi_dsi_video_packet_config(dsi, mode); > dw_mipi_dsi_command_mode_config(dsi); > - dw_mipi_dsi_line_timer_config(dsi); > - dw_mipi_dsi_vertical_timing_config(dsi); > + dw_mipi_dsi_line_timer_config(dsi, mode); > + dw_mipi_dsi_vertical_timing_config(dsi, mode); > dw_mipi_dsi_dphy_timing_config(dsi); > dw_mipi_dsi_dphy_interface_config(dsi); > dw_mipi_dsi_clear_err(dsi); > @@ -880,7 +883,7 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) > dev_err(dsi->dev, "failed to prepare panel\n"); > > dw_mipi_dsi_phy_init(dsi); > - dw_mipi_dsi_wait_for_two_frames(dsi); > + dw_mipi_dsi_wait_for_two_frames(mode); > > dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE); > drm_panel_enable(dsi->panel);