From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Zhong Subject: Re: [PATCH v2 10/26] drm/rockchip: dw-mipi-dsi: only request HS clock when required Date: Sun, 22 Jan 2017 16:10:36 +0800 Message-ID: <588468FC.7030906@rock-chips.com> References: <20170121163128.22240-1-john@metanate.com> <20170121163128.22240-11-john@metanate.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20170121163128.22240-11-john@metanate.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: John Keeping , Mark Yao Cc: linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org List-Id: linux-rockchip.vger.kernel.org SGkgSm9obgoKUmV2aWV3ZWQtYnk6IENocmlzIFpob25nIDx6eXdAcm9jay1jaGlwcy5jb20+CgpP biAwMS8yMi8yMDE3IDEyOjMxIEFNLCBKb2huIEtlZXBpbmcgd3JvdGU6Cj4gUmVxdWVzdGluZyB0 aGUgSFMgY2xvY2sgZnJvbSB0aGUgUEhZIGJlZm9yZSB3ZSBpbml0aWFsaXplIGl0IGNhdXNlcyBh bgo+IGludmFsaWQgc2lnbmFsIHRvIGJlIHNlbnQgb3V0IHNpbmNlIHRoZSBpbnB1dCBjbG9jayBp cyBub3QgeWV0Cj4gY29uZmlndXJlZC4gIFRoZSBQSFkgZGF0YWJvb2sgc3VnZ2VzdHMgb25seSBh c3NlcnRpbmcgdGhpcyBzaWduYWwgd2hlbgo+IHBlcmZvcm1pbmcgSFMgdHJhbnNmZXJzLCBzbyBs ZXQncyBkbyB0aGF0Lgo+Cj4gU2lnbmVkLW9mZi1ieTogSm9obiBLZWVwaW5nIDxqb2huQG1ldGFu YXRlLmNvbT4KPiAtLS0KPiBVbmNoYW5nZWQgaW4gdjIKPiAtLS0KPiAgIGRyaXZlcnMvZ3B1L2Ry bS9yb2NrY2hpcC9kdy1taXBpLWRzaS5jIHwgNiArKysrLS0KPiAgIDEgZmlsZSBjaGFuZ2VkLCA0 IGluc2VydGlvbnMoKyksIDIgZGVsZXRpb25zKC0pCj4KPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9n cHUvZHJtL3JvY2tjaGlwL2R3LW1pcGktZHNpLmMgYi9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAv ZHctbWlwaS1kc2kuYwo+IGluZGV4IDE1ZDMzYzNjOGNiNy4uMDNmYzA5NmZlMWJkIDEwMDY0NAo+ IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9kdy1taXBpLWRzaS5jCj4gKysrIGIvZHJp dmVycy9ncHUvZHJtL3JvY2tjaGlwL2R3LW1pcGktZHNpLmMKPiBAQCAtNTQ1LDEzICs1NDUsMTUg QEAgc3RhdGljIGludCBkd19taXBpX2RzaV9ob3N0X2RldGFjaChzdHJ1Y3QgbWlwaV9kc2lfaG9z dCAqaG9zdCwKPiAgIHN0YXRpYyB2b2lkIGR3X21pcGlfbWVzc2FnZV9jb25maWcoc3RydWN0IGR3 X21pcGlfZHNpICpkc2ksCj4gICAJCQkJICAgY29uc3Qgc3RydWN0IG1pcGlfZHNpX21zZyAqbXNn KQo+ICAgewo+ICsJYm9vbCBscG0gPSBtc2ctPmZsYWdzICYgTUlQSV9EU0lfTVNHX1VTRV9MUE07 Cj4gICAJdTMyIHZhbCA9IDA7Cj4gICAKPiAgIAlpZiAobXNnLT5mbGFncyAmIE1JUElfRFNJX01T R19SRVFfQUNLKQo+ICAgCQl2YWwgfD0gRU5fQUNLX1JRU1Q7Cj4gLQlpZiAobXNnLT5mbGFncyAm IE1JUElfRFNJX01TR19VU0VfTFBNKQo+ICsJaWYgKGxwbSkKPiAgIAkJdmFsIHw9IENNRF9NT0RF X0FMTF9MUDsKPiAgIAo+ICsJZHNpX3dyaXRlKGRzaSwgRFNJX0xQQ0xLX0NUUkwsIGxwbSA/IDAg OiBQSFlfVFhSRVFVRVNUQ0xLSFMpOwo+ICAgCWRzaV93cml0ZShkc2ksIERTSV9DTURfTU9ERV9D RkcsIHZhbCk7Cj4gICB9Cj4gICAKPiBAQCAtNjkzLDYgKzY5NSw3IEBAIHN0YXRpYyB2b2lkIGR3 X21pcGlfZHNpX3NldF9tb2RlKHN0cnVjdCBkd19taXBpX2RzaSAqZHNpLAo+ICAgCQlkc2lfd3Jp dGUoZHNpLCBEU0lfUFdSX1VQLCBSRVNFVCk7Cj4gICAJCWRzaV93cml0ZShkc2ksIERTSV9NT0RF X0NGRywgRU5BQkxFX1ZJREVPX01PREUpOwo+ICAgCQlkd19taXBpX2RzaV92aWRlb19tb2RlX2Nv bmZpZyhkc2kpOwo+ICsJCWRzaV93cml0ZShkc2ksIERTSV9MUENMS19DVFJMLCBQSFlfVFhSRVFV RVNUQ0xLSFMpOwo+ICAgCQlkc2lfd3JpdGUoZHNpLCBEU0lfUFdSX1VQLCBQT1dFUlVQKTsKPiAg IAl9Cj4gICB9Cj4gQEAgLTcxMCw3ICs3MTMsNiBAQCBzdGF0aWMgdm9pZCBkd19taXBpX2RzaV9p bml0KHN0cnVjdCBkd19taXBpX2RzaSAqZHNpKQo+ICAgCQkgIHwgUEhZX1JTVFogfCBQSFlfU0hV VERPV05aKTsKPiAgIAlkc2lfd3JpdGUoZHNpLCBEU0lfQ0xLTUdSX0NGRywgVE9fQ0xLX0RJVklE U0lPTigxMCkgfAo+ICAgCQkgIFRYX0VTQ19DTEtfRElWSURTSU9OKDcpKTsKPiAtCWRzaV93cml0 ZShkc2ksIERTSV9MUENMS19DVFJMLCBQSFlfVFhSRVFVRVNUQ0xLSFMpOwo+ICAgfQo+ICAgCj4g ICBzdGF0aWMgdm9pZCBkd19taXBpX2RzaV9kcGlfY29uZmlnKHN0cnVjdCBkd19taXBpX2RzaSAq ZHNpLAoKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmRy aS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRw czovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: zyw@rock-chips.com (Chris Zhong) Date: Sun, 22 Jan 2017 16:10:36 +0800 Subject: [PATCH v2 10/26] drm/rockchip: dw-mipi-dsi: only request HS clock when required In-Reply-To: <20170121163128.22240-11-john@metanate.com> References: <20170121163128.22240-1-john@metanate.com> <20170121163128.22240-11-john@metanate.com> Message-ID: <588468FC.7030906@rock-chips.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi John Reviewed-by: Chris Zhong On 01/22/2017 12:31 AM, John Keeping wrote: > Requesting the HS clock from the PHY before we initialize it causes an > invalid signal to be sent out since the input clock is not yet > configured. The PHY databook suggests only asserting this signal when > performing HS transfers, so let's do that. > > Signed-off-by: John Keeping > --- > Unchanged in v2 > --- > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > index 15d33c3c8cb7..03fc096fe1bd 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > @@ -545,13 +545,15 @@ static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host, > static void dw_mipi_message_config(struct dw_mipi_dsi *dsi, > const struct mipi_dsi_msg *msg) > { > + bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM; > u32 val = 0; > > if (msg->flags & MIPI_DSI_MSG_REQ_ACK) > val |= EN_ACK_RQST; > - if (msg->flags & MIPI_DSI_MSG_USE_LPM) > + if (lpm) > val |= CMD_MODE_ALL_LP; > > + dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS); > dsi_write(dsi, DSI_CMD_MODE_CFG, val); > } > > @@ -693,6 +695,7 @@ static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi, > dsi_write(dsi, DSI_PWR_UP, RESET); > dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE); > dw_mipi_dsi_video_mode_config(dsi); > + dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS); > dsi_write(dsi, DSI_PWR_UP, POWERUP); > } > } > @@ -710,7 +713,6 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) > | PHY_RSTZ | PHY_SHUTDOWNZ); > dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) | > TX_ESC_CLK_DIVIDSION(7)); > - dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS); > } > > static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751283AbdAVILg (ORCPT ); Sun, 22 Jan 2017 03:11:36 -0500 Received: from regular1.263xmail.com ([211.150.99.139]:47964 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750912AbdAVIL1 (ORCPT ); Sun, 22 Jan 2017 03:11:27 -0500 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-RL-SENDER: zyw@rock-chips.com X-FST-TO: linux-kernel@vger.kernel.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: zyw@rock-chips.com X-UNIQUE-TAG: <7199b3d73c6a362fb9246969110f1ab5> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH v2 10/26] drm/rockchip: dw-mipi-dsi: only request HS clock when required To: John Keeping , Mark Yao References: <20170121163128.22240-1-john@metanate.com> <20170121163128.22240-11-john@metanate.com> Cc: dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org From: Chris Zhong Message-ID: <588468FC.7030906@rock-chips.com> Date: Sun, 22 Jan 2017 16:10:36 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-Version: 1.0 In-Reply-To: <20170121163128.22240-11-john@metanate.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi John Reviewed-by: Chris Zhong On 01/22/2017 12:31 AM, John Keeping wrote: > Requesting the HS clock from the PHY before we initialize it causes an > invalid signal to be sent out since the input clock is not yet > configured. The PHY databook suggests only asserting this signal when > performing HS transfers, so let's do that. > > Signed-off-by: John Keeping > --- > Unchanged in v2 > --- > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > index 15d33c3c8cb7..03fc096fe1bd 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > @@ -545,13 +545,15 @@ static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host, > static void dw_mipi_message_config(struct dw_mipi_dsi *dsi, > const struct mipi_dsi_msg *msg) > { > + bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM; > u32 val = 0; > > if (msg->flags & MIPI_DSI_MSG_REQ_ACK) > val |= EN_ACK_RQST; > - if (msg->flags & MIPI_DSI_MSG_USE_LPM) > + if (lpm) > val |= CMD_MODE_ALL_LP; > > + dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS); > dsi_write(dsi, DSI_CMD_MODE_CFG, val); > } > > @@ -693,6 +695,7 @@ static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi, > dsi_write(dsi, DSI_PWR_UP, RESET); > dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE); > dw_mipi_dsi_video_mode_config(dsi); > + dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS); > dsi_write(dsi, DSI_PWR_UP, POWERUP); > } > } > @@ -710,7 +713,6 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) > | PHY_RSTZ | PHY_SHUTDOWNZ); > dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) | > TX_ESC_CLK_DIVIDSION(7)); > - dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS); > } > > static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,