From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Zhong Subject: Re: [PATCH v2 17/26] drm/rockchip: dw-mipi-dsi: don't enable PHY PLL until it's configured Date: Sun, 22 Jan 2017 18:07:38 +0800 Message-ID: <5884846A.7040200@rock-chips.com> References: <20170121163128.22240-1-john@metanate.com> <20170121163128.22240-18-john@metanate.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20170121163128.22240-18-john@metanate.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: John Keeping , Mark Yao Cc: linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org List-Id: linux-rockchip.vger.kernel.org SGkgSm9obgoKVGhpcyBwYXRjaCBkbyB0aGUgc2ltaWxhciB0aGluZyB3aXRoIApodHRwczovL3Bh dGNod29yay5rZXJuZWwub3JnL3BhdGNoLzk1MzA0MDUvClRoZXkgYXJlIGNoYW5naW5nIHRoZSBw aHkgY29uZmlndXJhdGlvbiBvcmRlciwgbXkgc3VnZ2VzdGlvbiBpcyB0byBtZXJnZSAKdGhlbS4K CgpPbiAwMS8yMi8yMDE3IDEyOjMxIEFNLCBKb2huIEtlZXBpbmcgd3JvdGU6Cj4gU2lnbmVkLW9m Zi1ieTogSm9obiBLZWVwaW5nIDxqb2huQG1ldGFuYXRlLmNvbT4KPiAtLS0KPiBVbmNoYW5nZWQg aW4gdjIKPiAtLS0KPiAgIGRyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9kdy1taXBpLWRzaS5jIHwg MiArLQo+ICAgMSBmaWxlIGNoYW5nZWQsIDEgaW5zZXJ0aW9uKCspLCAxIGRlbGV0aW9uKC0pCj4K PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL2R3LW1pcGktZHNpLmMgYi9k cml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvZHctbWlwaS1kc2kuYwo+IGluZGV4IGNlMWU2ZjlhMjA0 MS4uY2ZlN2U0YmEzMDVjIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9k dy1taXBpLWRzaS5jCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL2R3LW1pcGktZHNp LmMKPiBAQCAtNDEzLDEyICs0MTMsMTIgQEAgc3RhdGljIGludCBkd19taXBpX2RzaV9waHlfaW5p dChzdHJ1Y3QgZHdfbWlwaV9kc2kgKmRzaSkKPiAgIAo+ICAgCWR3X21pcGlfZHNpX3BoeV93cml0 ZShkc2ksIDB4NDQsIEhTRlJFUVJBTkdFX1NFTCh0ZXN0ZGluKSk7Cj4gICAKPiAtCWR3X21pcGlf ZHNpX3BoeV93cml0ZShkc2ksIDB4MTksIFBMTF9MT09QX0RJVl9FTiB8IFBMTF9JTlBVVF9ESVZf RU4pOwo+ICAgCWR3X21pcGlfZHNpX3BoeV93cml0ZShkc2ksIDB4MTcsIElOUFVUX0RJVklERVIo ZHNpLT5pbnB1dF9kaXYpKTsKPiAgIAlkd19taXBpX2RzaV9waHlfd3JpdGUoZHNpLCAweDE4LCBM T09QX0RJVl9MT1dfU0VMKGRzaS0+ZmVlZGJhY2tfZGl2KSB8Cj4gICAJCQkJCSBMT1dfUFJPR1JB TV9FTik7Cj4gICAJZHdfbWlwaV9kc2lfcGh5X3dyaXRlKGRzaSwgMHgxOCwgTE9PUF9ESVZfSElH SF9TRUwoZHNpLT5mZWVkYmFja19kaXYpIHwKPiAgIAkJCQkJIEhJR0hfUFJPR1JBTV9FTik7Cj4g Kwlkd19taXBpX2RzaV9waHlfd3JpdGUoZHNpLCAweDE5LCBQTExfTE9PUF9ESVZfRU4gfCBQTExf SU5QVVRfRElWX0VOKTsKPiAgIAo+ICAgCWR3X21pcGlfZHNpX3BoeV93cml0ZShkc2ksIDB4MjIs IExPV19QUk9HUkFNX0VOIHwKPiAgIAkJCQkJIEJJQVNFWFRSX1NFTChCSUFTRVhUUl8xMjdfNykp OwoKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1k ZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczov L2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: zyw@rock-chips.com (Chris Zhong) Date: Sun, 22 Jan 2017 18:07:38 +0800 Subject: [PATCH v2 17/26] drm/rockchip: dw-mipi-dsi: don't enable PHY PLL until it's configured In-Reply-To: <20170121163128.22240-18-john@metanate.com> References: <20170121163128.22240-1-john@metanate.com> <20170121163128.22240-18-john@metanate.com> Message-ID: <5884846A.7040200@rock-chips.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi John This patch do the similar thing with https://patchwork.kernel.org/patch/9530405/ They are changing the phy configuration order, my suggestion is to merge them. On 01/22/2017 12:31 AM, John Keeping wrote: > Signed-off-by: John Keeping > --- > Unchanged in v2 > --- > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > index ce1e6f9a2041..cfe7e4ba305c 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > @@ -413,12 +413,12 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) > > dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin)); > > - dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); > dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div)); > dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) | > LOW_PROGRAM_EN); > dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) | > HIGH_PROGRAM_EN); > + dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); > > dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN | > BIASEXTR_SEL(BIASEXTR_127_7)); From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751304AbdAVKKI (ORCPT ); Sun, 22 Jan 2017 05:10:08 -0500 Received: from regular1.263xmail.com ([211.150.99.132]:59077 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751000AbdAVKIq (ORCPT ); Sun, 22 Jan 2017 05:08:46 -0500 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-RL-SENDER: zyw@rock-chips.com X-FST-TO: linux-kernel@vger.kernel.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: zyw@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH v2 17/26] drm/rockchip: dw-mipi-dsi: don't enable PHY PLL until it's configured To: John Keeping , Mark Yao References: <20170121163128.22240-1-john@metanate.com> <20170121163128.22240-18-john@metanate.com> Cc: dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org From: Chris Zhong Message-ID: <5884846A.7040200@rock-chips.com> Date: Sun, 22 Jan 2017 18:07:38 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-Version: 1.0 In-Reply-To: <20170121163128.22240-18-john@metanate.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi John This patch do the similar thing with https://patchwork.kernel.org/patch/9530405/ They are changing the phy configuration order, my suggestion is to merge them. On 01/22/2017 12:31 AM, John Keeping wrote: > Signed-off-by: John Keeping > --- > Unchanged in v2 > --- > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > index ce1e6f9a2041..cfe7e4ba305c 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > @@ -413,12 +413,12 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) > > dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin)); > > - dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); > dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div)); > dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) | > LOW_PROGRAM_EN); > dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) | > HIGH_PROGRAM_EN); > + dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); > > dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN | > BIASEXTR_SEL(BIASEXTR_127_7));