From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Zhong Subject: Re: [PATCH v2 19/26] drm/rockchip: dw-mipi-dsi: improve PLL configuration Date: Mon, 23 Jan 2017 09:38:54 +0800 Message-ID: <58855EAE.2010704@rock-chips.com> References: <20170121163128.22240-1-john@metanate.com> <20170121163128.22240-20-john@metanate.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20170121163128.22240-20-john@metanate.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: John Keeping , Mark Yao Cc: linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org List-Id: linux-rockchip.vger.kernel.org SGkgSm9obgoKT24gMDEvMjIvMjAxNyAxMjozMSBBTSwgSm9obiBLZWVwaW5nIHdyb3RlOgo+IFRo ZSBtdWx0aXBsaWNhdGlvbiByYXRpbyBmb3IgdGhlIFBMTCBpcyByZXF1aXJlZCB0byBiZSBldmVu IGR1ZSB0byB0aGUKPiB1c2Ugb2YgYSAiYnkgMiBwcmUtc2NhbGVyIi4gIEN1cnJlbnRseSB3ZSBh cmUgbGlrZWx5IHRvIGVuZCB1cCB3aXRoIGFuCj4gb2RkIG11bHRpcGxpZXIgZXZlbiB0aG91Z2gg dGhlcmUgaXMgYW4gZXF1aXZhbGVudCBzZXQgb2YgcGFyYW1ldGVycyB3aXRoCj4gYW4gZXZlbiBt dWx0aXBsaWVyLgo+Cj4gRm9yIGV4YW1wbGUsIHVzaW5nIHRoZSAzMjRNSHogYml0IHJhdGUgd2l0 aCBhIHJlZmVyZW5jZSBjbG9jayBvZiAyNE1Iego+IHdlIGVuZCB1cCB3aXRoIE0gPSAyNywgTiA9 IDIgd2hlcmVhcyB0aGUgZXhhbXBsZSBpbiB0aGUgUEhZIGRhdGFib29rCj4gZ2l2ZXMgTSA9IDU0 LCBOID0gNCBmb3IgdGhpcyBiaXQgcmF0ZSBhbmQgcmVmZXJlbmNlIGNsb2NrLgo+Cj4gQnkgd2Fs a2luZyBkb3duIHRocm91Z2ggdGhlIGF2YWlsYWJsZSBtdWx0aXBsaWVyIGluc3RlYWQgb2YgdXAg d2UgYXJlCj4gbW9yZSBsaWtlbHkgdG8gaGl0IGFuIGV2ZW4gbXVsdGlwbGllci4gIFdpdGggdGhl IGFib3ZlIGV4YW1wbGUgd2UgZG8gbm93Cj4gZ2V0IE0gPSA1NCwgTiA9IDQgYXMgZ2l2ZW4gYnkg dGhlIGRhdGFib29rLgo+Cj4gV2hpbGUgZG9pbmcgdGhpcywgY2hhbmdlIHRoZSBsb29wIGxpbWl0 cyB0byBlbmNvZGUgdGhlIGFjdHVhbCBsaW1pdHMgb24KPiB0aGUgZGl2aXNvciwgd2hpY2ggYXJl Ogo+Cj4gCTQwTUh6ID49IChwbGxyZWYgLyBOKSA+PSA1TUh6CgpUaGlzIGZvcm11bGEgaXMgbGlt aXQgZm9yIE4sIGJ1dCB3ZSBzdGlsbCBjYW4gbm90IGd1YXJhbnRlZSB0byBnZXQgYW4gCmV2ZW4g TS4KRG8geW91IHRoaW5rIHdlIHNob3VsZCBkbyBhIGNoZWNrIGZvciBNLgpzdWNoIGFzOgppZiAo bSAlIDIpCiAgICAgY29udGludWU7Ci4uLgogICAgIGZvciAoaSA9IHBsbHJlZiAvIDU7IGkgPiAo cGxscmVmIC8gNDApOyBpLS0pIHsKICAgICAgICAgcHJlID0gcGxscmVmIC8gaTsKICAgICAgICAg aWYgKCh0bXAgPiAodGFyZ2V0X21icHMgJSBwcmUpKSAmJiAodGFyZ2V0X21icHMgLyBwcmUgPCA1 MTIpKSB7CiAgICAgICAgICAgICB0bXAgPSB0YXJnZXRfbWJwcyAlIHByZTsKICAgICAgICAgICAg IG4gPSBpOwogICAgICAgICAgICAgbSA9IHRhcmdldF9tYnBzIC8gcHJlOwogICAgICAgICAgICAg aWYgKG0gJSAyKQogICAgICAgICAgICAgICAgIGNvbnRpbnVlOwogICAgICAgICB9CiAgICAgICAg IGlmICh0bXAgPT0gMCkKICAgICAgICAgICAgIGJyZWFrOwogICAgIH0KCmlmIChtICUgMikKICAg ICBtKys7CgogICAgIGRzaS0+bGFuZV9tYnBzID0gcGxscmVmIC8gbiAqIG07CiAgICAgZHNpLT5p bnB1dF9kaXYgPSBuOwogICAgIGRzaS0+ZmVlZGJhY2tfZGl2ID0gbTsKCgoKPgo+IFNpZ25lZC1v ZmYtYnk6IEpvaG4gS2VlcGluZyA8am9obkBtZXRhbmF0ZS5jb20+Cj4gLS0tCj4gVW5jaGFuZ2Vk IGluIHYyCj4gLS0tCj4gICBkcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvZHctbWlwaS1kc2kuYyB8 IDIgKy0KPiAgIDEgZmlsZSBjaGFuZ2VkLCAxIGluc2VydGlvbigrKSwgMSBkZWxldGlvbigtKQo+ Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9kdy1taXBpLWRzaS5jIGIv ZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL2R3LW1pcGktZHNpLmMKPiBpbmRleCAxMjQzMmU0MTk3 MWIuLmYyMzIwY2YxMzY2YyAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAv ZHctbWlwaS1kc2kuYwo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9kdy1taXBpLWRz aS5jCj4gQEAgLTUxOSw3ICs1MTksNyBAQCBzdGF0aWMgaW50IGR3X21pcGlfZHNpX2dldF9sYW5l X2JwcyhzdHJ1Y3QgZHdfbWlwaV9kc2kgKmRzaSwKPiAgIAlwbGxyZWYgPSBESVZfUk9VTkRfVVAo Y2xrX2dldF9yYXRlKGRzaS0+cGxscmVmX2NsayksIFVTRUNfUEVSX1NFQyk7Cj4gICAJdG1wID0g cGxscmVmOwo+ICAgCj4gLQlmb3IgKGkgPSAxOyBpIDwgNjsgaSsrKSB7Cj4gKwlmb3IgKGkgPSBw bGxyZWYgLyA1OyBpID4gKHBsbHJlZiAvIDQwKTsgaS0tKSB7Cj4gICAJCXByZSA9IHBsbHJlZiAv IGk7Cj4gICAJCWlmICgodG1wID4gKHRhcmdldF9tYnBzICUgcHJlKSkgJiYgKHRhcmdldF9tYnBz IC8gcHJlIDwgNTEyKSkgewo+ICAgCQkJdG1wID0gdGFyZ2V0X21icHMgJSBwcmU7CgoKX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVsIG1haWxp bmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJl ZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: zyw@rock-chips.com (Chris Zhong) Date: Mon, 23 Jan 2017 09:38:54 +0800 Subject: [PATCH v2 19/26] drm/rockchip: dw-mipi-dsi: improve PLL configuration In-Reply-To: <20170121163128.22240-20-john@metanate.com> References: <20170121163128.22240-1-john@metanate.com> <20170121163128.22240-20-john@metanate.com> Message-ID: <58855EAE.2010704@rock-chips.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi John On 01/22/2017 12:31 AM, John Keeping wrote: > The multiplication ratio for the PLL is required to be even due to the > use of a "by 2 pre-scaler". Currently we are likely to end up with an > odd multiplier even though there is an equivalent set of parameters with > an even multiplier. > > For example, using the 324MHz bit rate with a reference clock of 24MHz > we end up with M = 27, N = 2 whereas the example in the PHY databook > gives M = 54, N = 4 for this bit rate and reference clock. > > By walking down through the available multiplier instead of up we are > more likely to hit an even multiplier. With the above example we do now > get M = 54, N = 4 as given by the databook. > > While doing this, change the loop limits to encode the actual limits on > the divisor, which are: > > 40MHz >= (pllref / N) >= 5MHz This formula is limit for N, but we still can not guarantee to get an even M. Do you think we should do a check for M. such as: if (m % 2) continue; ... for (i = pllref / 5; i > (pllref / 40); i--) { pre = pllref / i; if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) { tmp = target_mbps % pre; n = i; m = target_mbps / pre; if (m % 2) continue; } if (tmp == 0) break; } if (m % 2) m++; dsi->lane_mbps = pllref / n * m; dsi->input_div = n; dsi->feedback_div = m; > > Signed-off-by: John Keeping > --- > Unchanged in v2 > --- > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > index 12432e41971b..f2320cf1366c 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > @@ -519,7 +519,7 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi, > pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC); > tmp = pllref; > > - for (i = 1; i < 6; i++) { > + for (i = pllref / 5; i > (pllref / 40); i--) { > pre = pllref / i; > if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) { > tmp = target_mbps % pre; From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750815AbdAWBjo (ORCPT ); Sun, 22 Jan 2017 20:39:44 -0500 Received: from regular1.263xmail.com ([211.150.99.133]:55341 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750710AbdAWBjm (ORCPT ); Sun, 22 Jan 2017 20:39:42 -0500 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-RL-SENDER: zyw@rock-chips.com X-FST-TO: linux-kernel@vger.kernel.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: zyw@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH v2 19/26] drm/rockchip: dw-mipi-dsi: improve PLL configuration To: John Keeping , Mark Yao References: <20170121163128.22240-1-john@metanate.com> <20170121163128.22240-20-john@metanate.com> Cc: dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org From: Chris Zhong Message-ID: <58855EAE.2010704@rock-chips.com> Date: Mon, 23 Jan 2017 09:38:54 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-Version: 1.0 In-Reply-To: <20170121163128.22240-20-john@metanate.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi John On 01/22/2017 12:31 AM, John Keeping wrote: > The multiplication ratio for the PLL is required to be even due to the > use of a "by 2 pre-scaler". Currently we are likely to end up with an > odd multiplier even though there is an equivalent set of parameters with > an even multiplier. > > For example, using the 324MHz bit rate with a reference clock of 24MHz > we end up with M = 27, N = 2 whereas the example in the PHY databook > gives M = 54, N = 4 for this bit rate and reference clock. > > By walking down through the available multiplier instead of up we are > more likely to hit an even multiplier. With the above example we do now > get M = 54, N = 4 as given by the databook. > > While doing this, change the loop limits to encode the actual limits on > the divisor, which are: > > 40MHz >= (pllref / N) >= 5MHz This formula is limit for N, but we still can not guarantee to get an even M. Do you think we should do a check for M. such as: if (m % 2) continue; ... for (i = pllref / 5; i > (pllref / 40); i--) { pre = pllref / i; if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) { tmp = target_mbps % pre; n = i; m = target_mbps / pre; if (m % 2) continue; } if (tmp == 0) break; } if (m % 2) m++; dsi->lane_mbps = pllref / n * m; dsi->input_div = n; dsi->feedback_div = m; > > Signed-off-by: John Keeping > --- > Unchanged in v2 > --- > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > index 12432e41971b..f2320cf1366c 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > @@ -519,7 +519,7 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi, > pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC); > tmp = pllref; > > - for (i = 1; i < 6; i++) { > + for (i = pllref / 5; i > (pllref / 40); i--) { > pre = pllref / i; > if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) { > tmp = target_mbps % pre;