From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andres Rodriguez Subject: Shared semaphores for amdgpu Date: Thu, 5 Jan 2017 04:09:50 +0000 Message-ID: <544E607D03B20249AA404517E498FC469A558B@exchange01.valvesoftware.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1207213876==" Return-path: Content-Language: en-US List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: zhoucm1 , "Mao, David" , "Christian.Koenig-5C7GfCeVMHo@public.gmane.org" Cc: Dave Airlie , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" , Pierre-Loup Griffais --===============1207213876== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_544E607D03B20249AA404517E498FC469A558Bexchange01valveso_" --_000_544E607D03B20249AA404517E498FC469A558Bexchange01valveso_ Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable Hey guys, Just curious if there are any updates on the topic of shared semaphores for= amdgpu discussed here: https://lists.freedesktop.org/archives/amd-gfx/2016-December/003777.html I wasn't subscribed to amd-gfx yet when the topic started, so replying to i= t directly is cumbersome. Regards, Andres --_000_544E607D03B20249AA404517E498FC469A558Bexchange01valveso_ Content-Type: text/html; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable
Hey guys,

Just curious if there are any updates on the topic of shared semaphores for= amdgpu discussed here:
https://lists.freedesktop.org/archives/amd-gfx/= 2016-December/003777.html

I wasn't subscribed to amd-gfx yet when the topic started, so replying to i= t directly is cumbersome.

Regards,
Andres
--_000_544E607D03B20249AA404517E498FC469A558Bexchange01valveso_-- --===============1207213876== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KYW1kLWdmeCBt YWlsaW5nIGxpc3QKYW1kLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5m cmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9hbWQtZ2Z4Cg== --===============1207213876==-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Mao, David" Subject: RE: Shared semaphores for amdgpu Date: Thu, 5 Jan 2017 04:13:38 +0000 Message-ID: References: <544E607D03B20249AA404517E498FC469A558B@exchange01.valvesoftware.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0890408045==" Return-path: In-Reply-To: <544E607D03B20249AA404517E498FC469A558B-Lp/cVzEoVyaisxZYEgh0i620KmCxYQEWVpNB7YpNyf8@public.gmane.org> Content-Language: en-US List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: Andres Rodriguez , "Zhou, David(ChunMing)" , "Koenig, Christian" Cc: Dave Airlie , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" , Pierre-Loup Griffais --===============0890408045== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_BN4PR12MB0787AE3A185BE4D6916CE42AEE600BN4PR12MB0787namp_" --_000_BN4PR12MB0787AE3A185BE4D6916CE42AEE600BN4PR12MB0787namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Andres, We have a local change made yesterday which eliminate the need to get unuse= d fd in the creation time. If everything goes well, I expect the change could be sent out for review n= ext week. Best Regards, David From: Andres Rodriguez [mailto:andresr-38hxoXRICFZx67MzidHQgQC/G2K4zDHf@public.gmane.org] Sent: Thursday, January 5, 2017 12:10 PM To: Zhou, David(ChunMing) ; Mao, David ; Koenig, Christian Cc: Pierre-Loup Griffais ; Dave Airlie ; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Subject: Shared semaphores for amdgpu Hey guys, Just curious if there are any updates on the topic of shared semaphores for= amdgpu discussed here: https://lists.freedesktop.org/archives/amd-gfx/2016-December/003777.html I wasn't subscribed to amd-gfx yet when the topic started, so replying to i= t directly is cumbersome. Regards, Andres --_000_BN4PR12MB0787AE3A185BE4D6916CE42AEE600BN4PR12MB0787namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hi Andres,

We have a local change made yesterday= which eliminate the need to get unused fd in the creation time.=

If everything goes well, I expect the= change could be sent out for review next week.

 

Best Regards,

David

 

From: Andres Rodriguez [mailto:andre= sr-38hxoXRICFZx67MzidHQgQC/G2K4zDHf@public.gmane.org]
Sent: Thursday, January 5, 2017 12:10 PM
To: Zhou, David(ChunMing) <David1.Zhou-5C7GfCeVMHo@public.gmane.org>; Mao, David &l= t;David.Mao-5C7GfCeVMHo@public.gmane.org>; Koenig, Christian <Christian.Koenig-5C7GfCeVMHo@public.gmane.org>=
Cc: Pierre-Loup Griffais <pgriffais-38hxoXRICFZx67MzidHQgQC/G2K4zDHf@public.gmane.org>; Dave A= irlie <airlied-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Shared semaphores for amdgpu

 

Hey guys,

Just curious if there are any updates on the topic of shared semaphores for= amdgpu discussed here:
https://lists.freedesktop.org/archives/amd-gfx/= 2016-December/003777.html

I wasn't subscribed to amd-gfx yet when the topic started, so replying to i= t directly is cumbersome.

Regards,
Andres

--_000_BN4PR12MB0787AE3A185BE4D6916CE42AEE600BN4PR12MB0787namp_-- --===============0890408045== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KYW1kLWdmeCBt YWlsaW5nIGxpc3QKYW1kLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5m cmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9hbWQtZ2Z4Cg== --===============0890408045==-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andres Rodriguez Subject: Re: Shared semaphores for amdgpu Date: Thu, 5 Jan 2017 12:48:36 -0500 Message-ID: References: <544E607D03B20249AA404517E498FC469A558B@exchange01.valvesoftware.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1302418559==" Return-path: In-Reply-To: List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: "Mao, David" , Andres Rodriguez , "Zhou, David(ChunMing)" , "Koenig, Christian" Cc: Dave Airlie , Pierre-Loup Griffais , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" This is a multi-part message in MIME format. --===============1302418559== Content-Type: multipart/alternative; boundary="------------E3CB88839E55229FA96D0A2A" This is a multi-part message in MIME format. --------------E3CB88839E55229FA96D0A2A Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Cool, thanks for the heads up David. Regards, Andres On 1/4/2017 11:13 PM, Mao, David wrote: > > Hi Andres, > > We have a local change made yesterday which eliminate the need to get > unused fd in the creation time. > > If everything goes well, I expect the change could be sent out for > review next week. > > Best Regards, > > David > > *From:*Andres Rodriguez [mailto:andresr-38hxoXRICFZx67MzidHQgQC/G2K4zDHf@public.gmane.org] > *Sent:* Thursday, January 5, 2017 12:10 PM > *To:* Zhou, David(ChunMing) ; Mao, David > ; Koenig, Christian > *Cc:* Pierre-Loup Griffais ; Dave Airlie > ; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > *Subject:* Shared semaphores for amdgpu > > Hey guys, > > Just curious if there are any updates on the topic of shared > semaphores for amdgpu discussed here: > https://lists.freedesktop.org/archives/amd-gfx/2016-December/003777.html > > I wasn't subscribed to amd-gfx yet when the topic started, so replying > to it directly is cumbersome. > > Regards, > Andres > > > > _______________________________________________ > amd-gfx mailing list > amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx --------------E3CB88839E55229FA96D0A2A Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: 8bit

Cool, thanks for the heads up David.


Regards,

Andres


On 1/4/2017 11:13 PM, Mao, David wrote:

Hi Andres,

We have a local change made yesterday which eliminate the need to get unused fd in the creation time.

If everything goes well, I expect the change could be sent out for review next week.

 

Best Regards,

David

 

 

Hey guys,

Just curious if there are any updates on the topic of shared semaphores for amdgpu discussed here:
https://lists.freedesktop.org/archives/amd-gfx/2016-December/003777.html

I wasn't subscribed to amd-gfx yet when the topic started, so replying to it directly is cumbersome.

Regards,
Andres



_______________________________________________
amd-gfx mailing list
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

--------------E3CB88839E55229FA96D0A2A-- --===============1302418559== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KYW1kLWdmeCBt YWlsaW5nIGxpc3QKYW1kLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5m cmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9hbWQtZ2Z4Cg== --===============1302418559==-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dave Airlie Subject: Re: Shared semaphores for amdgpu Date: Tue, 28 Feb 2017 05:36:04 +1000 Message-ID: References: <544E607D03B20249AA404517E498FC469A558B@exchange01.valvesoftware.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: Andres Rodriguez Cc: "Zhou, David(ChunMing)" , "Mao, David" , Andres Rodriguez , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" , Dave Airlie , "Koenig, Christian" , Pierre-Loup Griffais SGksCgpBbnkgZnVydGhlciBuZXdzIG9uIHRoZXNlPwoKRGF2ZS4KCk9uIDYgSmFudWFyeSAyMDE3 IGF0IDAzOjQ4LCBBbmRyZXMgUm9kcmlndWV6IDxhbmRyZXN4N0BnbWFpbC5jb20+IHdyb3RlOgo+ IENvb2wsIHRoYW5rcyBmb3IgdGhlIGhlYWRzIHVwIERhdmlkLgo+Cj4KPiBSZWdhcmRzLAo+Cj4g QW5kcmVzCj4KPgo+IE9uIDEvNC8yMDE3IDExOjEzIFBNLCBNYW8sIERhdmlkIHdyb3RlOgo+Cj4g SGkgQW5kcmVzLAo+Cj4gV2UgaGF2ZSBhIGxvY2FsIGNoYW5nZSBtYWRlIHllc3RlcmRheSB3aGlj aCBlbGltaW5hdGUgdGhlIG5lZWQgdG8gZ2V0IHVudXNlZAo+IGZkIGluIHRoZSBjcmVhdGlvbiB0 aW1lLgo+Cj4gSWYgZXZlcnl0aGluZyBnb2VzIHdlbGwsIEkgZXhwZWN0IHRoZSBjaGFuZ2UgY291 bGQgYmUgc2VudCBvdXQgZm9yIHJldmlldwo+IG5leHQgd2Vlay4KPgo+Cj4KPiBCZXN0IFJlZ2Fy ZHMsCj4KPiBEYXZpZAo+Cj4KPgo+IEZyb206IEFuZHJlcyBSb2RyaWd1ZXogW21haWx0bzphbmRy ZXNyQHZhbHZlc29mdHdhcmUuY29tXQo+IFNlbnQ6IFRodXJzZGF5LCBKYW51YXJ5IDUsIDIwMTcg MTI6MTAgUE0KPiBUbzogWmhvdSwgRGF2aWQoQ2h1bk1pbmcpIDxEYXZpZDEuWmhvdUBhbWQuY29t PjsgTWFvLCBEYXZpZAo+IDxEYXZpZC5NYW9AYW1kLmNvbT47IEtvZW5pZywgQ2hyaXN0aWFuIDxD aHJpc3RpYW4uS29lbmlnQGFtZC5jb20+Cj4gQ2M6IFBpZXJyZS1Mb3VwIEdyaWZmYWlzIDxwZ3Jp ZmZhaXNAdmFsdmVzb2Z0d2FyZS5jb20+OyBEYXZlIEFpcmxpZQo+IDxhaXJsaWVkQHJlZGhhdC5j b20+OyBhbWQtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwo+IFN1YmplY3Q6IFNoYXJlZCBzZW1h cGhvcmVzIGZvciBhbWRncHUKPgo+Cj4KPiBIZXkgZ3V5cywKPgo+IEp1c3QgY3VyaW91cyBpZiB0 aGVyZSBhcmUgYW55IHVwZGF0ZXMgb24gdGhlIHRvcGljIG9mIHNoYXJlZCBzZW1hcGhvcmVzIGZv cgo+IGFtZGdwdSBkaXNjdXNzZWQgaGVyZToKPiBodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9y Zy9hcmNoaXZlcy9hbWQtZ2Z4LzIwMTYtRGVjZW1iZXIvMDAzNzc3Lmh0bWwKPgo+IEkgd2Fzbid0 IHN1YnNjcmliZWQgdG8gYW1kLWdmeCB5ZXQgd2hlbiB0aGUgdG9waWMgc3RhcnRlZCwgc28gcmVw bHlpbmcgdG8gaXQKPiBkaXJlY3RseSBpcyBjdW1iZXJzb21lLgo+Cj4gUmVnYXJkcywKPiBBbmRy ZXMKPgo+Cj4KPiBfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f Xwo+IGFtZC1nZnggbWFpbGluZyBsaXN0Cj4gYW1kLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcK PiBodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2FtZC1nZngK Pgo+Cj4KPiBfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwo+ IGFtZC1nZnggbWFpbGluZyBsaXN0Cj4gYW1kLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKPiBo dHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2FtZC1nZngKPgpf X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwphbWQtZ2Z4IG1h aWxpbmcgbGlzdAphbWQtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZy ZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2FtZC1nZngK From mboxrd@z Thu Jan 1 00:00:00 1970 From: zhoucm1 Subject: Re: Shared semaphores for amdgpu Date: Tue, 28 Feb 2017 09:46:54 +0800 Message-ID: <58B4D68E.5080606@amd.com> References: <544E607D03B20249AA404517E498FC469A558B@exchange01.valvesoftware.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="------------050002060306040803050803" Return-path: In-Reply-To: List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: Dave Airlie , Andres Rodriguez Cc: "Mao, David" , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" , Andres Rodriguez , Dave Airlie , "Cui, Flora" , "Koenig, Christian" , Pierre-Loup Griffais --------------050002060306040803050803 Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 8bit Hi Dave, The attached is our semaphore implementation, amdgpu_cs.c is drm file, the others are kernel file. Any suggestion? Regards, David Zhou On 2017年02月28日 03:36, Dave Airlie wrote: > Hi, > > Any further news on these? > > Dave. > > On 6 January 2017 at 03:48, Andres Rodriguez wrote: >> Cool, thanks for the heads up David. >> >> >> Regards, >> >> Andres >> >> >> On 1/4/2017 11:13 PM, Mao, David wrote: >> >> Hi Andres, >> >> We have a local change made yesterday which eliminate the need to get unused >> fd in the creation time. >> >> If everything goes well, I expect the change could be sent out for review >> next week. >> >> >> >> Best Regards, >> >> David >> >> >> >> From: Andres Rodriguez [mailto:andresr-38hxoXRICFZx67MzidHQgQC/G2K4zDHf@public.gmane.org] >> Sent: Thursday, January 5, 2017 12:10 PM >> To: Zhou, David(ChunMing) ; Mao, David >> ; Koenig, Christian >> Cc: Pierre-Loup Griffais ; Dave Airlie >> ; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org >> Subject: Shared semaphores for amdgpu >> >> >> >> Hey guys, >> >> Just curious if there are any updates on the topic of shared semaphores for >> amdgpu discussed here: >> https://lists.freedesktop.org/archives/amd-gfx/2016-December/003777.html >> >> I wasn't subscribed to amd-gfx yet when the topic started, so replying to it >> directly is cumbersome. >> >> Regards, >> Andres >> >> >> >> _______________________________________________ >> amd-gfx mailing list >> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx >> >> >> >> _______________________________________________ >> amd-gfx mailing list >> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx >> --------------050002060306040803050803 Content-Type: text/x-csrc; name="amdgpu_sem.c" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="amdgpu_sem.c" /* * Copyright 2016 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Chunming Zhou */ #include #include #include #include #include #include #include #include #include #include #include "amdgpu_sem.h" #include "amdgpu.h" #include static int amdgpu_sem_cring_add(struct amdgpu_fpriv *fpriv, struct drm_amdgpu_sem_in *in, struct amdgpu_sem *sem); static void amdgpu_sem_core_free(struct kref *kref) { struct amdgpu_sem_core *core = container_of( kref, struct amdgpu_sem_core, kref); if (core->file) fput(core->file); fence_put(core->fence); mutex_destroy(&core->lock); kfree(core); } static void amdgpu_sem_free(struct kref *kref) { struct amdgpu_sem *sem = container_of( kref, struct amdgpu_sem, kref); list_del(&sem->list); kref_put(&sem->base->kref, amdgpu_sem_core_free); kfree(sem); } static inline void amdgpu_sem_get(struct amdgpu_sem *sem) { if (sem) kref_get(&sem->kref); } static inline void amdgpu_sem_put(struct amdgpu_sem *sem) { if (sem) kref_put(&sem->kref, amdgpu_sem_free); } static int amdgpu_sem_release(struct inode *inode, struct file *file) { struct amdgpu_sem_core *core = file->private_data; kref_put(&core->kref, amdgpu_sem_core_free); return 0; } static unsigned int amdgpu_sem_poll(struct file *file, poll_table *wait) { return 0; } static long amdgpu_sem_file_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { return 0; } static const struct file_operations amdgpu_sem_fops = { .release = amdgpu_sem_release, .poll = amdgpu_sem_poll, .unlocked_ioctl = amdgpu_sem_file_ioctl, .compat_ioctl = amdgpu_sem_file_ioctl, }; static inline struct amdgpu_sem *amdgpu_sem_lookup(struct amdgpu_fpriv *fpriv, u32 handle) { struct amdgpu_sem *sem; spin_lock(&fpriv->sem_handles_lock); /* Check if we currently have a reference on the object */ sem = idr_find(&fpriv->sem_handles, handle); amdgpu_sem_get(sem); spin_unlock(&fpriv->sem_handles_lock); return sem; } static struct amdgpu_sem_core *amdgpu_sem_core_alloc(void) { struct amdgpu_sem_core *core; core = kzalloc(sizeof(*core), GFP_KERNEL); if (!core) return NULL; kref_init(&core->kref); mutex_init(&core->lock); return core; } static struct amdgpu_sem *amdgpu_sem_alloc(void) { struct amdgpu_sem *sem; sem = kzalloc(sizeof(*sem), GFP_KERNEL); if (!sem) return NULL; kref_init(&sem->kref); INIT_LIST_HEAD(&sem->list); return sem; } static int amdgpu_sem_create(struct amdgpu_fpriv *fpriv, u32 *handle) { struct amdgpu_sem *sem; struct amdgpu_sem_core *core; int ret; sem = amdgpu_sem_alloc(); core = amdgpu_sem_core_alloc(); if (!sem || !core) { kfree(sem); kfree(core); return -ENOMEM; } sem->base = core; idr_preload(GFP_KERNEL); spin_lock(&fpriv->sem_handles_lock); ret = idr_alloc(&fpriv->sem_handles, sem, 1, 0, GFP_NOWAIT); spin_unlock(&fpriv->sem_handles_lock); idr_preload_end(); if (ret < 0) return ret; *handle = ret; return 0; } static int amdgpu_sem_signal(struct amdgpu_fpriv *fpriv, u32 handle, struct fence *fence) { struct amdgpu_sem *sem; struct amdgpu_sem_core *core; sem = amdgpu_sem_lookup(fpriv, handle); if (!sem) return -EINVAL; core = sem->base; mutex_lock(&core->lock); fence_put(core->fence); core->fence = fence_get(fence); mutex_unlock(&core->lock); amdgpu_sem_put(sem); return 0; } static int amdgpu_sem_wait(struct amdgpu_fpriv *fpriv, struct drm_amdgpu_sem_in *in) { struct amdgpu_sem *sem; int ret; sem = amdgpu_sem_lookup(fpriv, in->handle); if (!sem) return -EINVAL; ret = amdgpu_sem_cring_add(fpriv, in, sem); amdgpu_sem_put(sem); return ret; } static int amdgpu_sem_import(struct amdgpu_fpriv *fpriv, int fd, u32 *handle) { struct file *file = fget(fd); struct amdgpu_sem *sem; struct amdgpu_sem_core *core; int ret; if (!file) return -EINVAL; core = file->private_data; if (!core) { fput(file); return -EINVAL; } mutex_lock(&core->lock); kref_get(&core->kref); mutex_unlock(&core->lock); sem = amdgpu_sem_alloc(); if (!sem) { ret = -ENOMEM; goto err_sem; } sem->base = core; idr_preload(GFP_KERNEL); spin_lock(&fpriv->sem_handles_lock); ret = idr_alloc(&fpriv->sem_handles, sem, 1, 0, GFP_NOWAIT); spin_unlock(&fpriv->sem_handles_lock); idr_preload_end(); if (ret < 0) goto err_out; *handle = ret; fput(file); return 0; err_sem: kref_put(&core->kref, amdgpu_sem_core_free); err_out: amdgpu_sem_put(sem); fput(file); return ret; } static int amdgpu_sem_export(struct amdgpu_fpriv *fpriv, u32 handle, int *fd) { struct amdgpu_sem *sem; struct amdgpu_sem_core *core; int ret; sem = amdgpu_sem_lookup(fpriv, handle); if (!sem) return -EINVAL; core = sem->base; mutex_lock(&core->lock); if (!core->file) { core->file = anon_inode_getfile("sem_file", &amdgpu_sem_fops, core, 0); if (IS_ERR(core->file)) { mutex_unlock(&core->lock); ret = -ENOMEM; goto err_put_sem; } } kref_get(&core->kref); mutex_unlock(&core->lock); ret = get_unused_fd_flags(O_CLOEXEC); if (ret < 0) goto err_put_file; fd_install(ret, core->file); *fd = ret; amdgpu_sem_put(sem); return 0; err_put_file: kref_put(&core->kref, amdgpu_sem_core_free); fput(core->file); err_put_sem: amdgpu_sem_put(sem); return ret; } void amdgpu_sem_destroy(struct amdgpu_fpriv *fpriv, u32 handle) { struct amdgpu_sem *sem = amdgpu_sem_lookup(fpriv, handle); if (!sem) return; spin_lock(&fpriv->sem_handles_lock); idr_remove(&fpriv->sem_handles, handle); spin_unlock(&fpriv->sem_handles_lock); kref_sub(&sem->kref, 2, amdgpu_sem_free); } static struct fence *amdgpu_sem_get_fence(struct amdgpu_fpriv *fpriv, struct drm_amdgpu_sem_in *in) { struct amdgpu_ring *out_ring; struct amdgpu_ctx *ctx; struct fence *fence; uint32_t ctx_id, ip_type, ip_instance, ring; int r; ctx_id = in->ctx_id; ip_type = in->ip_type; ip_instance = in->ip_instance; ring = in->ring; ctx = amdgpu_ctx_get(fpriv, ctx_id); if (!ctx) return NULL; r = amdgpu_cs_get_ring(ctx->adev, ip_type, ip_instance, ring, &out_ring); if (r) { amdgpu_ctx_put(ctx); return NULL; } /* get the last fence of this entity */ fence = amdgpu_ctx_get_fence(ctx, out_ring, in->seq ? in->seq : ctx->rings[out_ring->idx].sequence - 1); amdgpu_ctx_put(ctx); return fence; } static int amdgpu_sem_cring_add(struct amdgpu_fpriv *fpriv, struct drm_amdgpu_sem_in *in, struct amdgpu_sem *sem) { struct amdgpu_ring *out_ring; struct amdgpu_ctx *ctx; uint32_t ctx_id, ip_type, ip_instance, ring; int r; ctx_id = in->ctx_id; ip_type = in->ip_type; ip_instance = in->ip_instance; ring = in->ring; ctx = amdgpu_ctx_get(fpriv, ctx_id); if (!ctx) return -EINVAL; r = amdgpu_cs_get_ring(ctx->adev, ip_type, ip_instance, ring, &out_ring); if (r) goto err; mutex_lock(&ctx->rings[out_ring->idx].sem_lock); list_add(&sem->list, &ctx->rings[out_ring->idx].sem_list); mutex_unlock(&ctx->rings[out_ring->idx].sem_lock); err: amdgpu_ctx_put(ctx); return r; } int amdgpu_sem_add_cs(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, struct amdgpu_sync *sync) { struct amdgpu_sem *sem, *tmp; int r = 0; if (list_empty(&ctx->rings[ring->idx].sem_list)) return 0; mutex_lock(&ctx->rings[ring->idx].sem_lock); list_for_each_entry_safe(sem, tmp, &ctx->rings[ring->idx].sem_list, list) { r = amdgpu_sync_fence(ctx->adev, sync, sem->base->fence); if (r) goto err; mutex_lock(&sem->base->lock); fence_put(sem->base->fence); sem->base->fence = NULL; mutex_unlock(&sem->base->lock); list_del_init(&sem->list); } err: mutex_unlock(&ctx->rings[ring->idx].sem_lock); return r; } int amdgpu_sem_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { union drm_amdgpu_sem *args = data; struct amdgpu_fpriv *fpriv = filp->driver_priv; struct fence *fence; int r = 0; switch (args->in.op) { case AMDGPU_SEM_OP_CREATE_SEM: r = amdgpu_sem_create(fpriv, &args->out.handle); break; case AMDGPU_SEM_OP_WAIT_SEM: r = amdgpu_sem_wait(fpriv, &args->in); break; case AMDGPU_SEM_OP_SIGNAL_SEM: fence = amdgpu_sem_get_fence(fpriv, &args->in); if (IS_ERR(fence)) { r = PTR_ERR(fence); return r; } r = amdgpu_sem_signal(fpriv, args->in.handle, fence); fence_put(fence); break; case AMDGPU_SEM_OP_IMPORT_SEM: r = amdgpu_sem_import(fpriv, args->in.handle, &args->out.handle); break; case AMDGPU_SEM_OP_EXPORT_SEM: r = amdgpu_sem_export(fpriv, args->in.handle, &args->out.fd); break; case AMDGPU_SEM_OP_DESTROY_SEM: amdgpu_sem_destroy(fpriv, args->in.handle); break; default: r = -EINVAL; break; } return r; } --------------050002060306040803050803 Content-Type: text/x-chdr; name="amdgpu_sem.h" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="amdgpu_sem.h" /* * Copyright 2016 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Chunming Zhou * */ #ifndef _LINUX_AMDGPU_SEM_H #define _LINUX_AMDGPU_SEM_H #include #include #include #include #include #include struct amdgpu_sem_core { struct file *file; struct kref kref; struct fence *fence; struct mutex lock; }; struct amdgpu_sem { struct amdgpu_sem_core *base; struct kref kref; struct list_head list; }; #endif /* _LINUX_AMDGPU_SEM_H */ --------------050002060306040803050803 Content-Type: text/x-csrc; name="amdgpu_cs.c" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="amdgpu_cs.c" /* * Copyright 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include #include #include #include #include #include #include #include #include #ifdef HAVE_ALLOCA_H # include #endif #include "xf86drm.h" #include "amdgpu_drm.h" #include "amdgpu_internal.h" static int amdgpu_cs_unreference_sem(amdgpu_semaphore_handle sem); static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem); /** * Create command submission context * * \param dev - \c [in] amdgpu device handle * \param context - \c [out] amdgpu context handle * * \return 0 on success otherwise POSIX Error code */ int amdgpu_cs_ctx_create(amdgpu_device_handle dev, amdgpu_context_handle *context) { struct amdgpu_context *gpu_context; union drm_amdgpu_ctx args; int i, j, k; int r; if (NULL == dev) return -EINVAL; if (NULL == context) return -EINVAL; gpu_context = calloc(1, sizeof(struct amdgpu_context)); if (NULL == gpu_context) return -ENOMEM; gpu_context->dev = dev; r = pthread_mutex_init(&gpu_context->sequence_mutex, NULL); if (r) goto error; /* Create the context */ memset(&args, 0, sizeof(args)); args.in.op = AMDGPU_CTX_OP_ALLOC_CTX; r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CTX, &args, sizeof(args)); if (r) goto error; gpu_context->id = args.out.alloc.ctx_id; for (i = 0; i < AMDGPU_HW_IP_NUM; i++) for (j = 0; j < AMDGPU_HW_IP_INSTANCE_MAX_COUNT; j++) for (k = 0; k < AMDGPU_CS_MAX_RINGS; k++) list_inithead(&gpu_context->sem_list[i][j][k]); *context = (amdgpu_context_handle)gpu_context; return 0; error: pthread_mutex_destroy(&gpu_context->sequence_mutex); free(gpu_context); return r; } /** * Release command submission context * * \param dev - \c [in] amdgpu device handle * \param context - \c [in] amdgpu context handle * * \return 0 on success otherwise POSIX Error code */ int amdgpu_cs_ctx_free(amdgpu_context_handle context) { union drm_amdgpu_ctx args; int i, j, k; int r; if (NULL == context) return -EINVAL; pthread_mutex_destroy(&context->sequence_mutex); /* now deal with kernel side */ memset(&args, 0, sizeof(args)); args.in.op = AMDGPU_CTX_OP_FREE_CTX; args.in.ctx_id = context->id; r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX, &args, sizeof(args)); for (i = 0; i < AMDGPU_HW_IP_NUM; i++) { for (j = 0; j < AMDGPU_HW_IP_INSTANCE_MAX_COUNT; j++) { for (k = 0; k < AMDGPU_CS_MAX_RINGS; k++) { amdgpu_semaphore_handle sem; LIST_FOR_EACH_ENTRY(sem, &context->sem_list[i][j][k], list) { list_del(&sem->list); amdgpu_cs_reset_sem(sem); amdgpu_cs_unreference_sem(sem); } } } } free(context); return r; } int amdgpu_cs_query_reset_state(amdgpu_context_handle context, uint32_t *state, uint32_t *hangs) { union drm_amdgpu_ctx args; int r; if (!context) return -EINVAL; memset(&args, 0, sizeof(args)); args.in.op = AMDGPU_CTX_OP_QUERY_STATE; args.in.ctx_id = context->id; r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX, &args, sizeof(args)); if (!r) { *state = args.out.state.reset_status; *hangs = args.out.state.hangs; } return r; } /** * Submit command to kernel DRM * \param dev - \c [in] Device handle * \param context - \c [in] GPU Context * \param ibs_request - \c [in] Pointer to submission requests * \param fence - \c [out] return fence for this submission * * \return 0 on success otherwise POSIX Error code * \sa amdgpu_cs_submit() */ static int amdgpu_cs_submit_one(amdgpu_context_handle context, struct amdgpu_cs_request *ibs_request) { union drm_amdgpu_cs cs; uint64_t *chunk_array; struct drm_amdgpu_cs_chunk *chunks; struct drm_amdgpu_cs_chunk_data *chunk_data; struct drm_amdgpu_cs_chunk_dep *dependencies = NULL; struct drm_amdgpu_cs_chunk_dep *sem_dependencies = NULL; struct list_head *sem_list; amdgpu_semaphore_handle sem, tmp; uint32_t i, size, sem_count = 0; bool user_fence; int r = 0; if (ibs_request->ip_type >= AMDGPU_HW_IP_NUM) return -EINVAL; if (ibs_request->ring >= AMDGPU_CS_MAX_RINGS) return -EINVAL; if (ibs_request->number_of_ibs > AMDGPU_CS_MAX_IBS_PER_SUBMIT) return -EINVAL; if (ibs_request->number_of_ibs == 0) { ibs_request->seq_no = AMDGPU_NULL_SUBMIT_SEQ; return 0; } user_fence = (ibs_request->fence_info.handle != NULL); size = ibs_request->number_of_ibs + (user_fence ? 2 : 1) + 1; chunk_array = alloca(sizeof(uint64_t) * size); chunks = alloca(sizeof(struct drm_amdgpu_cs_chunk) * size); size = ibs_request->number_of_ibs + (user_fence ? 1 : 0); chunk_data = alloca(sizeof(struct drm_amdgpu_cs_chunk_data) * size); memset(&cs, 0, sizeof(cs)); cs.in.chunks = (uint64_t)(uintptr_t)chunk_array; cs.in.ctx_id = context->id; if (ibs_request->resources) cs.in.bo_list_handle = ibs_request->resources->handle; cs.in.num_chunks = ibs_request->number_of_ibs; /* IB chunks */ for (i = 0; i < ibs_request->number_of_ibs; i++) { struct amdgpu_cs_ib_info *ib; chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i]; chunks[i].chunk_id = AMDGPU_CHUNK_ID_IB; chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4; chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i]; ib = &ibs_request->ibs[i]; chunk_data[i].ib_data._pad = 0; chunk_data[i].ib_data.va_start = ib->ib_mc_address; chunk_data[i].ib_data.ib_bytes = ib->size * 4; chunk_data[i].ib_data.ip_type = ibs_request->ip_type; chunk_data[i].ib_data.ip_instance = ibs_request->ip_instance; chunk_data[i].ib_data.ring = ibs_request->ring; chunk_data[i].ib_data.flags = ib->flags; } pthread_mutex_lock(&context->sequence_mutex); if (user_fence) { i = cs.in.num_chunks++; /* fence chunk */ chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i]; chunks[i].chunk_id = AMDGPU_CHUNK_ID_FENCE; chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_fence) / 4; chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i]; /* fence bo handle */ chunk_data[i].fence_data.handle = ibs_request->fence_info.handle->handle; /* offset */ chunk_data[i].fence_data.offset = ibs_request->fence_info.offset * sizeof(uint64_t); } if (ibs_request->number_of_dependencies) { dependencies = malloc(sizeof(struct drm_amdgpu_cs_chunk_dep) * ibs_request->number_of_dependencies); if (!dependencies) { r = -ENOMEM; goto error_unlock; } for (i = 0; i < ibs_request->number_of_dependencies; ++i) { struct amdgpu_cs_fence *info = &ibs_request->dependencies[i]; struct drm_amdgpu_cs_chunk_dep *dep = &dependencies[i]; dep->ip_type = info->ip_type; dep->ip_instance = info->ip_instance; dep->ring = info->ring; dep->ctx_id = info->context->id; dep->handle = info->fence; } i = cs.in.num_chunks++; /* dependencies chunk */ chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i]; chunks[i].chunk_id = AMDGPU_CHUNK_ID_DEPENDENCIES; chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_dep) / 4 * ibs_request->number_of_dependencies; chunks[i].chunk_data = (uint64_t)(uintptr_t)dependencies; } sem_list = &context->sem_list[ibs_request->ip_type][ibs_request->ip_instance][ibs_request->ring]; LIST_FOR_EACH_ENTRY(sem, sem_list, list) sem_count++; if (sem_count) { sem_dependencies = malloc(sizeof(struct drm_amdgpu_cs_chunk_dep) * sem_count); if (!sem_dependencies) { r = -ENOMEM; goto error_unlock; } sem_count = 0; LIST_FOR_EACH_ENTRY_SAFE(sem, tmp, sem_list, list) { struct amdgpu_cs_fence *info = &sem->signal_fence; struct drm_amdgpu_cs_chunk_dep *dep = &sem_dependencies[sem_count++]; dep->ip_type = info->ip_type; dep->ip_instance = info->ip_instance; dep->ring = info->ring; dep->ctx_id = info->context->id; dep->handle = info->fence; list_del(&sem->list); amdgpu_cs_reset_sem(sem); amdgpu_cs_unreference_sem(sem); } i = cs.in.num_chunks++; /* dependencies chunk */ chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i]; chunks[i].chunk_id = AMDGPU_CHUNK_ID_DEPENDENCIES; chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_dep) / 4 * sem_count; chunks[i].chunk_data = (uint64_t)(uintptr_t)sem_dependencies; } r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CS, &cs, sizeof(cs)); if (r) goto error_unlock; ibs_request->seq_no = cs.out.handle; context->last_seq[ibs_request->ip_type][ibs_request->ip_instance][ibs_request->ring] = ibs_request->seq_no; error_unlock: pthread_mutex_unlock(&context->sequence_mutex); free(dependencies); free(sem_dependencies); return r; } int amdgpu_cs_submit(amdgpu_context_handle context, uint64_t flags, struct amdgpu_cs_request *ibs_request, uint32_t number_of_requests) { uint32_t i; int r; if (NULL == context) return -EINVAL; if (NULL == ibs_request) return -EINVAL; r = 0; for (i = 0; i < number_of_requests; i++) { r = amdgpu_cs_submit_one(context, ibs_request); if (r) break; ibs_request++; } return r; } /** * Calculate absolute timeout. * * \param timeout - \c [in] timeout in nanoseconds. * * \return absolute timeout in nanoseconds */ drm_private uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout) { int r; if (timeout != AMDGPU_TIMEOUT_INFINITE) { struct timespec current; uint64_t current_ns; r = clock_gettime(CLOCK_MONOTONIC, ¤t); if (r) { fprintf(stderr, "clock_gettime() returned error (%d)!", errno); return AMDGPU_TIMEOUT_INFINITE; } current_ns = ((uint64_t)current.tv_sec) * 1000000000ull; current_ns += current.tv_nsec; timeout += current_ns; if (timeout < current_ns) timeout = AMDGPU_TIMEOUT_INFINITE; } return timeout; } static int amdgpu_ioctl_wait_cs(amdgpu_context_handle context, unsigned ip, unsigned ip_instance, uint32_t ring, uint64_t handle, uint64_t timeout_ns, uint64_t flags, bool *busy) { amdgpu_device_handle dev = context->dev; union drm_amdgpu_wait_cs args; int r; memset(&args, 0, sizeof(args)); args.in.handle = handle; args.in.ip_type = ip; args.in.ip_instance = ip_instance; args.in.ring = ring; args.in.ctx_id = context->id; if (flags & AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE) args.in.timeout = timeout_ns; else args.in.timeout = amdgpu_cs_calculate_timeout(timeout_ns); r = drmIoctl(dev->fd, DRM_IOCTL_AMDGPU_WAIT_CS, &args); if (r) return -errno; *busy = args.out.status; return 0; } int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, uint64_t timeout_ns, uint64_t flags, uint32_t *expired) { bool busy = true; int r; if (NULL == fence) return -EINVAL; if (NULL == expired) return -EINVAL; if (NULL == fence->context) return -EINVAL; if (fence->ip_type >= AMDGPU_HW_IP_NUM) return -EINVAL; if (fence->ring >= AMDGPU_CS_MAX_RINGS) return -EINVAL; if (fence->fence == AMDGPU_NULL_SUBMIT_SEQ) { *expired = true; return 0; } *expired = false; r = amdgpu_ioctl_wait_cs(fence->context, fence->ip_type, fence->ip_instance, fence->ring, fence->fence, timeout_ns, flags, &busy); if (!r && !busy) *expired = true; return r; } static int amdgpu_ioctl_wait_fences(struct amdgpu_cs_fence *fences, uint32_t fence_count, bool wait_all, uint64_t timeout_ns, uint32_t *status, uint32_t *first) { struct drm_amdgpu_fence *drm_fences; amdgpu_device_handle dev = fences[0].context->dev; union drm_amdgpu_wait_fences args; int r; uint32_t i; drm_fences = alloca(sizeof(struct drm_amdgpu_fence) * fence_count); for (i = 0; i < fence_count; i++) { drm_fences[i].ctx_id = fences[i].context->id; drm_fences[i].ip_type = fences[i].ip_type; drm_fences[i].ip_instance = fences[i].ip_instance; drm_fences[i].ring = fences[i].ring; drm_fences[i].seq_no = fences[i].fence; } memset(&args, 0, sizeof(args)); args.in.fences = (uint64_t)(uintptr_t)drm_fences; args.in.fence_count = fence_count; args.in.wait_all = wait_all; args.in.timeout_ns = amdgpu_cs_calculate_timeout(timeout_ns); r = drmIoctl(dev->fd, DRM_IOCTL_AMDGPU_WAIT_FENCES, &args); if (r) return -errno; *status = args.out.status; if (first) *first = args.out.first_signaled; return 0; } int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, uint32_t fence_count, bool wait_all, uint64_t timeout_ns, uint32_t *status, uint32_t *first) { uint32_t ioctl_status = 0; uint32_t i; int r; /* Sanity check */ if (NULL == fences) return -EINVAL; if (NULL == status) return -EINVAL; if (fence_count <= 0) return -EINVAL; for (i = 0; i < fence_count; i++) { if (NULL == fences[i].context) return -EINVAL; if (fences[i].ip_type >= AMDGPU_HW_IP_NUM) return -EINVAL; if (fences[i].ring >= AMDGPU_CS_MAX_RINGS) return -EINVAL; } *status = 0; r = amdgpu_ioctl_wait_fences(fences, fence_count, wait_all, timeout_ns, &ioctl_status, first); if (!r) *status = ioctl_status; return r; } int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem) { struct amdgpu_semaphore *gpu_semaphore; if (NULL == sem) return -EINVAL; gpu_semaphore = calloc(1, sizeof(struct amdgpu_semaphore)); if (NULL == gpu_semaphore) return -ENOMEM; atomic_set(&gpu_semaphore->refcount, 1); *sem = gpu_semaphore; return 0; } int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx, uint32_t ip_type, uint32_t ip_instance, uint32_t ring, amdgpu_semaphore_handle sem) { if (NULL == ctx) return -EINVAL; if (ip_type >= AMDGPU_HW_IP_NUM) return -EINVAL; if (ring >= AMDGPU_CS_MAX_RINGS) return -EINVAL; if (NULL == sem) return -EINVAL; /* sem has been signaled */ if (sem->signal_fence.context) return -EINVAL; pthread_mutex_lock(&ctx->sequence_mutex); sem->signal_fence.context = ctx; sem->signal_fence.ip_type = ip_type; sem->signal_fence.ip_instance = ip_instance; sem->signal_fence.ring = ring; sem->signal_fence.fence = ctx->last_seq[ip_type][ip_instance][ring]; update_references(NULL, &sem->refcount); pthread_mutex_unlock(&ctx->sequence_mutex); return 0; } int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, uint32_t ip_type, uint32_t ip_instance, uint32_t ring, amdgpu_semaphore_handle sem) { if (NULL == ctx) return -EINVAL; if (ip_type >= AMDGPU_HW_IP_NUM) return -EINVAL; if (ring >= AMDGPU_CS_MAX_RINGS) return -EINVAL; if (NULL == sem) return -EINVAL; /* must signal first */ if (NULL == sem->signal_fence.context) return -EINVAL; pthread_mutex_lock(&ctx->sequence_mutex); list_add(&sem->list, &ctx->sem_list[ip_type][ip_instance][ring]); pthread_mutex_unlock(&ctx->sequence_mutex); return 0; } static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem) { if (NULL == sem) return -EINVAL; if (NULL == sem->signal_fence.context) return -EINVAL; sem->signal_fence.context = NULL;; sem->signal_fence.ip_type = 0; sem->signal_fence.ip_instance = 0; sem->signal_fence.ring = 0; sem->signal_fence.fence = 0; return 0; } static int amdgpu_cs_unreference_sem(amdgpu_semaphore_handle sem) { if (NULL == sem) return -EINVAL; if (update_references(&sem->refcount, NULL)) free(sem); return 0; } int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem) { return amdgpu_cs_unreference_sem(sem); } int amdgpu_cs_create_sem(amdgpu_device_handle dev, amdgpu_sem_handle *sem) { union drm_amdgpu_sem args; int r; if (NULL == dev) return -EINVAL; /* Create the context */ memset(&args, 0, sizeof(args)); args.in.op = AMDGPU_SEM_OP_CREATE_SEM; r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args)); if (r) return r; *sem = args.out.handle; return 0; } int amdgpu_cs_signal_sem(amdgpu_device_handle dev, amdgpu_context_handle ctx, uint32_t ip_type, uint32_t ip_instance, uint32_t ring, amdgpu_sem_handle sem) { union drm_amdgpu_sem args; if (NULL == dev) return -EINVAL; /* Create the context */ memset(&args, 0, sizeof(args)); args.in.op = AMDGPU_SEM_OP_SIGNAL_SEM; args.in.ctx_id = ctx->id; args.in.ip_type = ip_type; args.in.ip_instance = ip_instance; args.in.ring = ring; args.in.handle = sem; return drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args)); } int amdgpu_cs_wait_sem(amdgpu_device_handle dev, amdgpu_context_handle ctx, uint32_t ip_type, uint32_t ip_instance, uint32_t ring, amdgpu_sem_handle sem) { union drm_amdgpu_sem args; if (NULL == dev) return -EINVAL; /* Create the context */ memset(&args, 0, sizeof(args)); args.in.op = AMDGPU_SEM_OP_WAIT_SEM; args.in.ctx_id = ctx->id; args.in.ip_type = ip_type; args.in.ip_instance = ip_instance; args.in.ring = ring; args.in.handle = sem; args.in.seq = 0; return drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args)); } int amdgpu_cs_export_sem(amdgpu_device_handle dev, amdgpu_sem_handle sem, int *shared_handle) { union drm_amdgpu_sem args; int r; if (NULL == dev) return -EINVAL; /* Create the context */ memset(&args, 0, sizeof(args)); args.in.op = AMDGPU_SEM_OP_EXPORT_SEM; args.in.handle = sem; r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args)); if (r) return r; *shared_handle = args.out.fd; return 0; } int amdgpu_cs_import_sem(amdgpu_device_handle dev, int shared_handle, amdgpu_sem_handle *sem) { union drm_amdgpu_sem args; int r; if (NULL == dev) return -EINVAL; /* Create the context */ memset(&args, 0, sizeof(args)); args.in.op = AMDGPU_SEM_OP_IMPORT_SEM; args.in.handle = shared_handle; r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args)); if (r) return r; *sem = args.out.handle; return 0; } int amdgpu_cs_destroy_sem(amdgpu_device_handle dev, amdgpu_sem_handle sem) { union drm_amdgpu_sem args; int r; if (NULL == dev) return -EINVAL; /* Create the context */ memset(&args, 0, sizeof(args)); args.in.op = AMDGPU_SEM_OP_DESTROY_SEM; args.in.handle = sem; r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args)); if (r) return r; return 0; } --------------050002060306040803050803 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KYW1kLWdmeCBt YWlsaW5nIGxpc3QKYW1kLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5m cmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9hbWQtZ2Z4Cg== --------------050002060306040803050803-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dave Airlie Subject: Re: Shared semaphores for amdgpu Date: Thu, 9 Mar 2017 13:52:06 +1000 Message-ID: References: <544E607D03B20249AA404517E498FC469A558B@exchange01.valvesoftware.com> <58B4D68E.5080606@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <58B4D68E.5080606-5C7GfCeVMHo@public.gmane.org> List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: zhoucm1 Cc: "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" , "Mao, David" , Andres Rodriguez , Andres Rodriguez , Dave Airlie , "Cui, Flora" , "Koenig, Christian" , Pierre-Loup Griffais T24gMjggRmVicnVhcnkgMjAxNyBhdCAxMTo0NiwgemhvdWNtMSA8ZGF2aWQxLnpob3VAYW1kLmNv bT4gd3JvdGU6Cj4gSGkgRGF2ZSwKPgo+IFRoZSBhdHRhY2hlZCBpcyBvdXIgc2VtYXBob3JlIGlt cGxlbWVudGF0aW9uLCBhbWRncHVfY3MuYyBpcyBkcm0gZmlsZSwgdGhlCj4gb3RoZXJzIGFyZSBr ZXJuZWwgZmlsZS4KPiBBbnkgc3VnZ2VzdGlvbj8KVGhhbmtzLAoKSSd2ZSBidWlsdCBhIHRyZWUg d2l0aCBhbGwgdGhlc2UgaW4gaXQsIGFuZCBzdGFydGVkIGxvb2tpbmcgaW50byB0aGUgaW50ZXJm YWNlLgoKSSBkbyB3b25kZXIgaWYgd2UgbmVlZCB0aGUgc2VwYXJhdGUgc2VtIHNpZ25hbC93YWl0 IGludGVyZmFjZSwgSSB0aGluawp3ZSBzaG91bGQganVzdCBhZGQKc2VtYXBob3JlIGNodW5rcyB0 byB0aGUgQ1MgaW50ZXJmYWNlLgoKSSdtIGp1c3QgcGxheWluZyBhcm91bmQgd2l0aCB0aGlzIG5v dy4KCkRhdmUuCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f CmFtZC1nZnggbWFpbGluZyBsaXN0CmFtZC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBz Oi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vYW1kLWdmeAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dave Airlie Subject: Re: Shared semaphores for amdgpu Date: Thu, 9 Mar 2017 14:24:37 +1000 Message-ID: References: <544E607D03B20249AA404517E498FC469A558B@exchange01.valvesoftware.com> <58B4D68E.5080606@amd.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary=f403045f87327fc8d3054a449fd5 Return-path: In-Reply-To: List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: zhoucm1 Cc: "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" , "Mao, David" , Andres Rodriguez , Andres Rodriguez , Dave Airlie , "Cui, Flora" , "Koenig, Christian" , Pierre-Loup Griffais --f403045f87327fc8d3054a449fd5 Content-Type: text/plain; charset=UTF-8 I've attached two patches for RFC at the moment, I haven't finished the userspace for these yet, but just wanted to get some ideas/feedback. Dave. On 9 March 2017 at 13:52, Dave Airlie wrote: > On 28 February 2017 at 11:46, zhoucm1 wrote: >> Hi Dave, >> >> The attached is our semaphore implementation, amdgpu_cs.c is drm file, the >> others are kernel file. >> Any suggestion? > Thanks, > > I've built a tree with all these in it, and started looking into the interface. > > I do wonder if we need the separate sem signal/wait interface, I think > we should just add > semaphore chunks to the CS interface. > > I'm just playing around with this now. > > Dave. --f403045f87327fc8d3054a449fd5 Content-Type: text/x-patch; charset=US-ASCII; name="0001-amdgpu-cs-split-out-fence-dependency-checking.patch" Content-Disposition: attachment; filename="0001-amdgpu-cs-split-out-fence-dependency-checking.patch" Content-Transfer-Encoding: base64 X-Attachment-Id: f_j01w2lnw0 RnJvbSA2Njg1MmQzZTFkYzQyNDIxZWIxY2ZkOTY0MGMwNDNiYmE3MDkzMWFmIE1vbiBTZXAgMTcg MDA6MDA6MDAgMjAwMQpGcm9tOiBEYXZlIEFpcmxpZSA8YWlybGllZEByZWRoYXQuY29tPgpEYXRl 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SUIJCTB4MDEKICNkZWZpbmUgQU1ER1BVX0NIVU5LX0lEX0ZFTkNFCQkweDAyCiAjZGVmaW5lIEFN REdQVV9DSFVOS19JRF9ERVBFTkRFTkNJRVMJMHgwMworI2RlZmluZSBBTURHUFVfQ0hVTktfSURf U0VNX1dBSVQgICAgICAgIDB4MDQKKyNkZWZpbmUgQU1ER1BVX0NIVU5LX0lEX1NFTV9TSUdOQUwg ICAgICAweDA1CiAKIHN0cnVjdCBkcm1fYW1kZ3B1X2NzX2NodW5rIHsKIAlfX3UzMgkJY2h1bmtf aWQ7Ci0tIAoyLjcuNAoK --f403045f87327fc8d3054a449fd5 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KYW1kLWdmeCBt YWlsaW5nIGxpc3QKYW1kLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5m cmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9hbWQtZ2Z4Cg== --f403045f87327fc8d3054a449fd5-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: zhoucm1 Subject: Re: Shared semaphores for amdgpu Date: Thu, 9 Mar 2017 15:00:22 +0800 Message-ID: <58C0FD86.8040808@amd.com> References: <544E607D03B20249AA404517E498FC469A558B@exchange01.valvesoftware.com> <58B4D68E.5080606@amd.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="------------040601090507040301020506" Return-path: In-Reply-To: List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: Dave Airlie Cc: "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" , "Mao, David" , Andres Rodriguez , Andres Rodriguez , Dave Airlie , "Cui, Flora" , "Koenig, Christian" , Pierre-Loup Griffais --------------040601090507040301020506 Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit Hi Dave, We have already completed implementation as the attached for both kernel and libdrm. We discuss it on top of this. Thanks, David Zhou On 2017年03月09日 12:24, Dave Airlie wrote: > I've attached two patches for RFC at the moment, I haven't finished > the userspace for these yet, but just wanted to get some > ideas/feedback. > > Dave. > > On 9 March 2017 at 13:52, Dave Airlie wrote: >> On 28 February 2017 at 11:46, zhoucm1 wrote: >>> Hi Dave, >>> >>> The attached is our semaphore implementation, amdgpu_cs.c is drm file, the >>> others are kernel file. >>> Any suggestion? >> Thanks, >> >> I've built a tree with all these in it, and started looking into the interface. >> >> I do wonder if we need the separate sem signal/wait interface, I think >> we should just add >> semaphore chunks to the CS interface. >> >> I'm just playing around with this now. >> >> Dave. --------------040601090507040301020506 Content-Type: text/x-patch; name="0001-drm-amdgpu-add-new-semaphore-object-in-kernel-side-V.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename*0="0001-drm-amdgpu-add-new-semaphore-object-in-kernel-side-V.pa"; filename*1="tch" >>From 030ab323340d5557cd0ccf07d41f932b762745ac Mon Sep 17 00:00:00 2001 From: Chunming Zhou Date: Fri, 23 Sep 2016 10:22:22 +0800 Subject: [PATCH] drm/amdgpu: add new semaphore object in kernel side V3 So that semaphore can be shared across porcess across devices. V2: add import/export V3: some bug fixes Signed-off-by: Chunming Zhou (v1, v3) Signed-off-by: Flora Cui (v2) Reviewed-by: Monk Liu (v1) Acked-by: Hawking Zhang (v2) Reviewed-by: David Mao (v3) Change-Id: I88e2168328d005a42b41eb7b0c60530a92126829 --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 13 + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 6 +- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 10 +- drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c | 444 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h | 50 ++++ include/uapi/drm/amdgpu_drm.h | 32 +++ 8 files changed, 555 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 8870e2e..0075287 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -30,7 +30,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \ atombios_encoders.o amdgpu_sa.o atombios_i2c.o \ amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \ amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \ - amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o + amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_sem.o # add asic specific block amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 4435b36..d3b1593 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -56,6 +56,7 @@ #include "amdgpu_sync.h" #include "amdgpu_ring.h" #include "amdgpu_vm.h" +#include "amdgpu_sem.h" #include "amd_powerplay.h" #include "amdgpu_dpm.h" #include "amdgpu_acp.h" @@ -665,6 +666,8 @@ struct amdgpu_ctx_ring { uint64_t sequence; struct fence **fences; struct amd_sched_entity entity; + struct list_head sem_list; + struct mutex sem_lock; }; struct amdgpu_ctx { @@ -708,6 +711,8 @@ struct amdgpu_fpriv { struct mutex bo_list_lock; struct idr bo_list_handles; struct amdgpu_ctx_mgr ctx_mgr; + spinlock_t sem_handles_lock; + struct idr sem_handles; }; /* @@ -1243,6 +1248,14 @@ int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, int amdgpu_freesync_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); +int amdgpu_sem_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); + +int amdgpu_sem_add_cs(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, + struct amdgpu_sync *sync); + +void amdgpu_sem_destroy(struct amdgpu_fpriv *fpriv, u32 handle); + /* VRAM scratch page for HDP bug, default vram page */ struct amdgpu_vram_scratch { struct amdgpu_bo *robj; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index aafe11e..92b1423 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1024,7 +1024,7 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev, } } - return 0; + return amdgpu_sem_add_cs(p->ctx, p->job->ring, &p->job->sync); } static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index 6d86eae..66cf23c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -42,6 +42,8 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, struct amdgpu_ctx *ctx) for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { ctx->rings[i].sequence = 1; ctx->rings[i].fences = &ctx->fences[amdgpu_sched_jobs * i]; + INIT_LIST_HEAD(&ctx->rings[i].sem_list); + mutex_init(&ctx->rings[i].sem_lock); } ctx->reset_counter = atomic_read(&adev->gpu_reset_counter); @@ -78,8 +80,10 @@ static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx) return; for (i = 0; i < AMDGPU_MAX_RINGS; ++i) - for (j = 0; j < amdgpu_sched_jobs; ++j) + for (j = 0; j < amdgpu_sched_jobs; ++j) { fence_put(ctx->rings[i].fences[j]); + mutex_destroy(&ctx->rings[i].sem_lock); + } kfree(ctx->fences); ctx->fences = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index ee3720e..b973225 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -749,6 +749,8 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) mutex_init(&fpriv->bo_list_lock); idr_init(&fpriv->bo_list_handles); + spin_lock_init(&fpriv->sem_handles_lock); + idr_init(&fpriv->sem_handles); amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); @@ -775,6 +777,7 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, struct amdgpu_device *adev = dev->dev_private; struct amdgpu_fpriv *fpriv = file_priv->driver_priv; struct amdgpu_bo_list *list; + struct amdgpu_sem *sem; int handle; if (!fpriv) @@ -803,6 +806,10 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, idr_destroy(&fpriv->bo_list_handles); mutex_destroy(&fpriv->bo_list_lock); + idr_for_each_entry(&fpriv->sem_handles, sem, handle) + amdgpu_sem_destroy(fpriv, handle); + idr_destroy(&fpriv->sem_handles); + kfree(fpriv); file_priv->driver_priv = NULL; @@ -984,7 +991,8 @@ int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(AMDGPU_FREESYNC, amdgpu_freesync_ioctl, DRM_MASTER) + DRM_IOCTL_DEF_DRV(AMDGPU_FREESYNC, amdgpu_freesync_ioctl, DRM_MASTER), + DRM_IOCTL_DEF_DRV(AMDGPU_SEM, amdgpu_sem_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), }; const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c new file mode 100644 index 0000000..6681162 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c @@ -0,0 +1,444 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Chunming Zhou + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "amdgpu_sem.h" +#include "amdgpu.h" +#include + +static int amdgpu_sem_cring_add(struct amdgpu_fpriv *fpriv, + struct drm_amdgpu_sem_in *in, + struct amdgpu_sem *sem); + +static void amdgpu_sem_core_free(struct kref *kref) +{ + struct amdgpu_sem_core *core = container_of( + kref, struct amdgpu_sem_core, kref); + + fence_put(core->fence); + mutex_destroy(&core->lock); + kfree(core); +} + +static void amdgpu_sem_free(struct kref *kref) +{ + struct amdgpu_sem *sem = container_of( + kref, struct amdgpu_sem, kref); + + list_del(&sem->list); + kref_put(&sem->base->kref, amdgpu_sem_core_free); + kfree(sem); +} + +static inline void amdgpu_sem_get(struct amdgpu_sem *sem) +{ + if (sem) + kref_get(&sem->kref); +} + +static inline void amdgpu_sem_put(struct amdgpu_sem *sem) +{ + if (sem) + kref_put(&sem->kref, amdgpu_sem_free); +} + +static int amdgpu_sem_release(struct inode *inode, struct file *file) +{ + struct amdgpu_sem_core *core = file->private_data; + + kref_put(&core->kref, amdgpu_sem_core_free); + return 0; +} + +static unsigned int amdgpu_sem_poll(struct file *file, poll_table *wait) +{ + return 0; +} + +static long amdgpu_sem_file_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + return 0; +} + +static const struct file_operations amdgpu_sem_fops = { + .release = amdgpu_sem_release, + .poll = amdgpu_sem_poll, + .unlocked_ioctl = amdgpu_sem_file_ioctl, + .compat_ioctl = amdgpu_sem_file_ioctl, +}; + + +static inline struct amdgpu_sem *amdgpu_sem_lookup(struct amdgpu_fpriv *fpriv, u32 handle) +{ + struct amdgpu_sem *sem; + + spin_lock(&fpriv->sem_handles_lock); + + /* Check if we currently have a reference on the object */ + sem = idr_find(&fpriv->sem_handles, handle); + amdgpu_sem_get(sem); + + spin_unlock(&fpriv->sem_handles_lock); + + return sem; +} + +static struct amdgpu_sem_core *amdgpu_sem_core_alloc(void) +{ + struct amdgpu_sem_core *core; + + core = kzalloc(sizeof(*core), GFP_KERNEL); + if (!core) + return NULL; + + kref_init(&core->kref); + mutex_init(&core->lock); + return core; +} + +static struct amdgpu_sem *amdgpu_sem_alloc(void) +{ + struct amdgpu_sem *sem; + + sem = kzalloc(sizeof(*sem), GFP_KERNEL); + if (!sem) + return NULL; + + kref_init(&sem->kref); + INIT_LIST_HEAD(&sem->list); + + return sem; +} + +static int amdgpu_sem_create(struct amdgpu_fpriv *fpriv, u32 *handle) +{ + struct amdgpu_sem *sem; + struct amdgpu_sem_core *core; + int ret; + + sem = amdgpu_sem_alloc(); + core = amdgpu_sem_core_alloc(); + if (!sem || !core) { + kfree(sem); + kfree(core); + return -ENOMEM; + } + + sem->base = core; + + idr_preload(GFP_KERNEL); + spin_lock(&fpriv->sem_handles_lock); + + ret = idr_alloc(&fpriv->sem_handles, sem, 1, 0, GFP_NOWAIT); + + spin_unlock(&fpriv->sem_handles_lock); + idr_preload_end(); + + if (ret < 0) + return ret; + + *handle = ret; + return 0; +} + +static int amdgpu_sem_signal(struct amdgpu_fpriv *fpriv, + u32 handle, struct fence *fence) +{ + struct amdgpu_sem *sem; + struct amdgpu_sem_core *core; + + sem = amdgpu_sem_lookup(fpriv, handle); + if (!sem) + return -EINVAL; + + core = sem->base; + mutex_lock(&core->lock); + fence_put(core->fence); + core->fence = fence_get(fence); + mutex_unlock(&core->lock); + + amdgpu_sem_put(sem); + return 0; +} + +static int amdgpu_sem_wait(struct amdgpu_fpriv *fpriv, + struct drm_amdgpu_sem_in *in) +{ + struct amdgpu_sem *sem; + int ret; + + sem = amdgpu_sem_lookup(fpriv, in->handle); + if (!sem) + return -EINVAL; + + ret = amdgpu_sem_cring_add(fpriv, in, sem); + amdgpu_sem_put(sem); + + return ret; +} + +static int amdgpu_sem_import(struct amdgpu_fpriv *fpriv, + int fd, u32 *handle) +{ + struct file *file = fget(fd); + struct amdgpu_sem *sem; + struct amdgpu_sem_core *core; + int ret; + + if (!file) + return -EINVAL; + + core = file->private_data; + if (!core) { + fput(file); + return -EINVAL; + } + + kref_get(&core->kref); + sem = amdgpu_sem_alloc(); + if (!sem) { + ret = -ENOMEM; + goto err_sem; + } + + sem->base = core; + + idr_preload(GFP_KERNEL); + spin_lock(&fpriv->sem_handles_lock); + + ret = idr_alloc(&fpriv->sem_handles, sem, 1, 0, GFP_NOWAIT); + + spin_unlock(&fpriv->sem_handles_lock); + idr_preload_end(); + + if (ret < 0) + goto err_out; + + *handle = ret; + fput(file); + return 0; +err_sem: + kref_put(&core->kref, amdgpu_sem_core_free); +err_out: + amdgpu_sem_put(sem); + fput(file); + return ret; + +} + +static int amdgpu_sem_export(struct amdgpu_fpriv *fpriv, + u32 handle, int *fd) +{ + struct amdgpu_sem *sem; + struct amdgpu_sem_core *core; + int ret; + + sem = amdgpu_sem_lookup(fpriv, handle); + if (!sem) + return -EINVAL; + + core = sem->base; + kref_get(&core->kref); + mutex_lock(&core->lock); + if (!core->file) { + core->file = anon_inode_getfile("sem_file", + &amdgpu_sem_fops, + core, 0); + if (IS_ERR(core->file)) { + mutex_unlock(&core->lock); + ret = -ENOMEM; + goto err_put_sem; + } + } else { + get_file(core->file); + } + mutex_unlock(&core->lock); + + ret = get_unused_fd_flags(O_CLOEXEC); + if (ret < 0) + goto err_put_file; + + fd_install(ret, core->file); + + *fd = ret; + amdgpu_sem_put(sem); + return 0; + +err_put_file: + fput(core->file); +err_put_sem: + kref_put(&core->kref, amdgpu_sem_core_free); + amdgpu_sem_put(sem); + return ret; +} + +void amdgpu_sem_destroy(struct amdgpu_fpriv *fpriv, u32 handle) +{ + struct amdgpu_sem *sem = amdgpu_sem_lookup(fpriv, handle); + if (!sem) + return; + + spin_lock(&fpriv->sem_handles_lock); + idr_remove(&fpriv->sem_handles, handle); + spin_unlock(&fpriv->sem_handles_lock); + + kref_sub(&sem->kref, 2, amdgpu_sem_free); +} + +static struct fence *amdgpu_sem_get_fence(struct amdgpu_fpriv *fpriv, + struct drm_amdgpu_sem_in *in) +{ + struct amdgpu_ring *out_ring; + struct amdgpu_ctx *ctx; + struct fence *fence; + uint32_t ctx_id, ip_type, ip_instance, ring; + int r; + + ctx_id = in->ctx_id; + ip_type = in->ip_type; + ip_instance = in->ip_instance; + ring = in->ring; + ctx = amdgpu_ctx_get(fpriv, ctx_id); + if (!ctx) + return NULL; + r = amdgpu_cs_get_ring(ctx->adev, ip_type, ip_instance, ring, + &out_ring); + if (r) { + amdgpu_ctx_put(ctx); + return NULL; + } + /* get the last fence of this entity */ + fence = amdgpu_ctx_get_fence(ctx, out_ring, + in->seq ? in->seq : + ctx->rings[out_ring->idx].sequence - 1); + amdgpu_ctx_put(ctx); + + return fence; +} + +static int amdgpu_sem_cring_add(struct amdgpu_fpriv *fpriv, + struct drm_amdgpu_sem_in *in, + struct amdgpu_sem *sem) +{ + struct amdgpu_ring *out_ring; + struct amdgpu_ctx *ctx; + uint32_t ctx_id, ip_type, ip_instance, ring; + int r; + + ctx_id = in->ctx_id; + ip_type = in->ip_type; + ip_instance = in->ip_instance; + ring = in->ring; + ctx = amdgpu_ctx_get(fpriv, ctx_id); + if (!ctx) + return -EINVAL; + r = amdgpu_cs_get_ring(ctx->adev, ip_type, ip_instance, ring, + &out_ring); + if (r) + goto err; + mutex_lock(&ctx->rings[out_ring->idx].sem_lock); + list_add(&sem->list, &ctx->rings[out_ring->idx].sem_list); + mutex_unlock(&ctx->rings[out_ring->idx].sem_lock); + +err: + amdgpu_ctx_put(ctx); + return r; +} + +int amdgpu_sem_add_cs(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, + struct amdgpu_sync *sync) +{ + struct amdgpu_sem *sem, *tmp; + int r = 0; + + if (list_empty(&ctx->rings[ring->idx].sem_list)) + return 0; + + mutex_lock(&ctx->rings[ring->idx].sem_lock); + list_for_each_entry_safe(sem, tmp, &ctx->rings[ring->idx].sem_list, + list) { + r = amdgpu_sync_fence(ctx->adev, sync, sem->base->fence); + if (r) + goto err; + mutex_lock(&sem->base->lock); + fence_put(sem->base->fence); + sem->base->fence = NULL; + mutex_unlock(&sem->base->lock); + list_del_init(&sem->list); + } +err: + mutex_unlock(&ctx->rings[ring->idx].sem_lock); + return r; +} + +int amdgpu_sem_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + union drm_amdgpu_sem *args = data; + struct amdgpu_fpriv *fpriv = filp->driver_priv; + struct fence *fence; + int r = 0; + + switch (args->in.op) { + case AMDGPU_SEM_OP_CREATE_SEM: + r = amdgpu_sem_create(fpriv, &args->out.handle); + break; + case AMDGPU_SEM_OP_WAIT_SEM: + r = amdgpu_sem_wait(fpriv, &args->in); + break; + case AMDGPU_SEM_OP_SIGNAL_SEM: + fence = amdgpu_sem_get_fence(fpriv, &args->in); + if (IS_ERR(fence)) { + r = PTR_ERR(fence); + return r; + } + r = amdgpu_sem_signal(fpriv, args->in.handle, fence); + fence_put(fence); + break; + case AMDGPU_SEM_OP_IMPORT_SEM: + r = amdgpu_sem_import(fpriv, args->in.handle, &args->out.handle); + break; + case AMDGPU_SEM_OP_EXPORT_SEM: + r = amdgpu_sem_export(fpriv, args->in.handle, &args->out.fd); + break; + case AMDGPU_SEM_OP_DESTROY_SEM: + amdgpu_sem_destroy(fpriv, args->in.handle); + break; + default: + r = -EINVAL; + break; + } + + return r; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h new file mode 100644 index 0000000..04296ca --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h @@ -0,0 +1,50 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Chunming Zhou + * + */ + + +#ifndef _LINUX_AMDGPU_SEM_H +#define _LINUX_AMDGPU_SEM_H + +#include +#include +#include +#include +#include +#include + +struct amdgpu_sem_core { + struct file *file; + struct kref kref; + struct fence *fence; + struct mutex lock; +}; + +struct amdgpu_sem { + struct amdgpu_sem_core *base; + struct kref kref; + struct list_head list; +}; + +#endif /* _LINUX_AMDGPU_SEM_H */ diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 49358e7..d17f431 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -53,6 +53,8 @@ #define DRM_AMDGPU_WAIT_FENCES 0x12 #define DRM_AMDGPU_FREESYNC 0x14 +#define DRM_AMDGPU_SEM 0x5b + #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) @@ -67,6 +69,7 @@ #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) #define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) +#define DRM_IOCTL_AMDGPU_SEM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_SEM, union drm_amdgpu_sem) #define AMDGPU_GEM_DOMAIN_CPU 0x1 #define AMDGPU_GEM_DOMAIN_GTT 0x2 @@ -192,6 +195,35 @@ struct drm_amdgpu_ctx_in { union drm_amdgpu_ctx_out out; }; +/* sem related */ +#define AMDGPU_SEM_OP_CREATE_SEM 1 +#define AMDGPU_SEM_OP_WAIT_SEM 2 +#define AMDGPU_SEM_OP_SIGNAL_SEM 3 +#define AMDGPU_SEM_OP_DESTROY_SEM 4 +#define AMDGPU_SEM_OP_IMPORT_SEM 5 +#define AMDGPU_SEM_OP_EXPORT_SEM 6 + +struct drm_amdgpu_sem_in { + /** AMDGPU_SEM_OP_* */ + uint32_t op; + uint32_t handle; + uint32_t ctx_id; + uint32_t ip_type; + uint32_t ip_instance; + uint32_t ring; + uint64_t seq; +}; + +union drm_amdgpu_sem_out { + int32_t fd; + uint32_t handle; +}; + +union drm_amdgpu_sem { + struct drm_amdgpu_sem_in in; + union drm_amdgpu_sem_out out; +}; + /* * This is not a reliable API and you should expect it to fail for any * number of reasons and have fallback path that do not use userptr to -- 1.9.1 --------------040601090507040301020506 Content-Type: text/x-patch; name="0001-amdgpu-add-new-semaphore-support-v2.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="0001-amdgpu-add-new-semaphore-support-v2.patch" >>From ec6e6f599fe61537ed42b9953126691f904626d4 Mon Sep 17 00:00:00 2001 From: Chunming Zhou Date: Thu, 22 Sep 2016 14:50:16 +0800 Subject: [PATCH 1/2] amdgpu: add new semaphore support v2 v2: add import/export functions. Change-Id: I74b61611e975d6f2de051e3f3c7ba63177308bdb Signed-off-by: Chunming Zhou (v1) Reviewed-by: Monk Liu (v1) Signed-off-by: Flora Cui (v2) Acked-by: Hawking Zhang (v2) --- amdgpu/amdgpu.h | 82 ++++++++++++++++++++++++++++- amdgpu/amdgpu_cs.c | 133 +++++++++++++++++++++++++++++++++++++++++++++++ include/drm/amdgpu_drm.h | 34 ++++++++++++ 3 files changed, 248 insertions(+), 1 deletion(-) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index 941406e..eb75283 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -151,6 +151,12 @@ typedef struct amdgpu_ib *amdgpu_ib_handle; */ typedef struct amdgpu_va *amdgpu_va_handle; +/** + * Define handle for sem file + */ +typedef uint32_t amdgpu_sem_handle; + + /*--------------------------------------------------------------------------*/ /* -------------------------- Structures ---------------------------------- */ /*--------------------------------------------------------------------------*/ @@ -1336,6 +1342,80 @@ int amdgpu_va_range_alloc(enum amdgpu_gpu_va_range va_range_type, */ int amdgpu_va_range_free(amdgpu_va_handle va_range_handle); -#endif /* #ifdef _amdgpu_h_ */ +/** + * create sem + * + * \param dev - [in] Device handle. See #amdgpu_device_initialize() + * \param sem - \c [out] sem handle + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_cs_create_sem(amdgpu_device_handle dev, + amdgpu_sem_handle *sem); + +/** + * signal sem + * + * \param dev - [in] Device handle. See #amdgpu_device_initialize() + * \param context - \c [in] GPU Context + * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* + * \param ip_instance - \c [in] Index of the IP block of the same type + * \param ring - \c [in] Specify ring index of the IP + * \param sem - \c [out] sem handle + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * + */ +int amdgpu_cs_signal_sem(amdgpu_device_handle dev, + amdgpu_context_handle ctx, + uint32_t ip_type, + uint32_t ip_instance, + uint32_t ring, + amdgpu_sem_handle sem); + +/** + * wait sem + * + * \param dev - [in] Device handle. See #amdgpu_device_initialize() + * \param context - \c [in] GPU Context + * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* + * \param ip_instance - \c [in] Index of the IP block of the same type + * \param ring - \c [in] Specify ring index of the IP + * \param sem - \c [out] sem handle + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_cs_wait_sem(amdgpu_device_handle dev, + amdgpu_context_handle ctx, + uint32_t ip_type, + uint32_t ip_instance, + uint32_t ring, + amdgpu_sem_handle sem); + +int amdgpu_cs_export_sem(amdgpu_device_handle dev, + amdgpu_sem_handle sem, + int *shared_handle); +int amdgpu_cs_import_sem(amdgpu_device_handle dev, + int shared_handle, + amdgpu_sem_handle *sem); +/** + * destroy sem + * + * \param dev - [in] Device handle. See #amdgpu_device_initialize() + * \param sem - \c [out] sem handle + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * + */ +int amdgpu_cs_destroy_sem(amdgpu_device_handle dev, + amdgpu_sem_handle sem); + +#endif /* #ifdef _amdgpu_h_ */ diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c index c8101b8..c8d8593 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c @@ -20,6 +20,9 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ + +#include +#include #include #include #include @@ -913,3 +916,133 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_query_fence *fence, return r; } +int amdgpu_cs_create_sem(amdgpu_device_handle dev, + amdgpu_sem_handle *sem) +{ + union drm_amdgpu_sem args; + int r; + + if (NULL == dev) + return -EINVAL; + + /* Create the context */ + memset(&args, 0, sizeof(args)); + args.in.op = AMDGPU_SEM_OP_CREATE_SEM; + r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args)); + if (r) + return r; + + *sem = args.out.handle; + + return 0; +} + +int amdgpu_cs_signal_sem(amdgpu_device_handle dev, + amdgpu_context_handle ctx, + uint32_t ip_type, + uint32_t ip_instance, + uint32_t ring, + amdgpu_sem_handle sem) +{ + union drm_amdgpu_sem args; + + if (NULL == dev) + return -EINVAL; + + /* Create the context */ + memset(&args, 0, sizeof(args)); + args.in.op = AMDGPU_SEM_OP_SIGNAL_SEM; + args.in.ctx_id = ctx->id; + args.in.ip_type = ip_type; + args.in.ip_instance = ip_instance; + args.in.ring = ring; + args.in.handle = sem; + return drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args)); +} + +int amdgpu_cs_wait_sem(amdgpu_device_handle dev, + amdgpu_context_handle ctx, + uint32_t ip_type, + uint32_t ip_instance, + uint32_t ring, + amdgpu_sem_handle sem) +{ + union drm_amdgpu_sem args; + + if (NULL == dev) + return -EINVAL; + + /* Create the context */ + memset(&args, 0, sizeof(args)); + args.in.op = AMDGPU_SEM_OP_WAIT_SEM; + args.in.ctx_id = ctx->id; + args.in.ip_type = ip_type; + args.in.ip_instance = ip_instance; + args.in.ring = ring; + args.in.handle = sem; + args.in.seq = 0; + return drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args)); +} + +int amdgpu_cs_export_sem(amdgpu_device_handle dev, + amdgpu_sem_handle sem, + int *shared_handle) +{ + union drm_amdgpu_sem args; + int r; + + if (NULL == dev) + return -EINVAL; + + /* Create the context */ + memset(&args, 0, sizeof(args)); + args.in.op = AMDGPU_SEM_OP_EXPORT_SEM; + args.in.handle = sem; + r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args)); + if (r) + return r; + *shared_handle = args.out.fd; + return 0; +} + +int amdgpu_cs_import_sem(amdgpu_device_handle dev, + int shared_handle, + amdgpu_sem_handle *sem) +{ + union drm_amdgpu_sem args; + int r; + + if (NULL == dev) + return -EINVAL; + + /* Create the context */ + memset(&args, 0, sizeof(args)); + args.in.op = AMDGPU_SEM_OP_IMPORT_SEM; + args.in.handle = shared_handle; + r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args)); + if (r) + return r; + *sem = args.out.handle; + return 0; +} + + +int amdgpu_cs_destroy_sem(amdgpu_device_handle dev, + amdgpu_sem_handle sem) +{ + union drm_amdgpu_sem args; + int r; + + if (NULL == dev) + return -EINVAL; + + /* Create the context */ + memset(&args, 0, sizeof(args)); + args.in.op = AMDGPU_SEM_OP_DESTROY_SEM; + args.in.handle = sem; + r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args)); + if (r) + return r; + + return 0; +} diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index 89a938a..ccd9033 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -46,6 +46,9 @@ #define DRM_AMDGPU_WAIT_CS 0x09 #define DRM_AMDGPU_GEM_OP 0x10 #define DRM_AMDGPU_GEM_USERPTR 0x11 +#define DRM_AMDGPU_WAIT_FENCES 0x12 + +#define DRM_AMDGPU_SEM 0x5b #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) @@ -59,6 +62,8 @@ #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) +#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) +#define DRM_IOCTL_AMDGPU_SEM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_SEM, union drm_amdgpu_sem) #define AMDGPU_GEM_DOMAIN_CPU 0x1 #define AMDGPU_GEM_DOMAIN_GTT 0x2 @@ -182,6 +187,35 @@ union drm_amdgpu_ctx { union drm_amdgpu_ctx_out out; }; +/* sync file related */ +#define AMDGPU_SEM_OP_CREATE_SEM 1 +#define AMDGPU_SEM_OP_WAIT_SEM 2 +#define AMDGPU_SEM_OP_SIGNAL_SEM 3 +#define AMDGPU_SEM_OP_DESTROY_SEM 4 +#define AMDGPU_SEM_OP_IMPORT_SEM 5 +#define AMDGPU_SEM_OP_EXPORT_SEM 6 + +struct drm_amdgpu_sem_in { + /** AMDGPU_SEM_OP_* */ + uint32_t op; + uint32_t handle; + uint32_t ctx_id; + uint32_t ip_type; + uint32_t ip_instance; + uint32_t ring; + uint64_t seq; +}; + +union drm_amdgpu_sem_out { + int fd; + uint32_t handle; +}; + +union drm_amdgpu_sem { + struct drm_amdgpu_sem_in in; + union drm_amdgpu_sem_out out; +}; + /* * This is not a reliable API and you should expect it to fail for any * number of reasons and have fallback path that do not use userptr to -- 1.9.1 --------------040601090507040301020506 Content-Type: text/x-patch; name="0002-test-case-for-export-import-sem.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="0002-test-case-for-export-import-sem.patch" >>From 1d391323c06c03a90b1d349f8a8c79a29af8fc90 Mon Sep 17 00:00:00 2001 From: David Mao Date: Mon, 23 Jan 2017 11:31:58 +0800 Subject: [PATCH 2/2] test case for export/import sem Test covers basic functionality includes create/destroy/import/export/wait/signal Change-Id: I8a8d767e5ef1889f8ac214fef98befba83969d8d Signed-off-by: David Mao Signed-off-by: Flora Cui Acked-by: Hawking Zhang --- tests/amdgpu/basic_tests.c | 190 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 190 insertions(+) diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 0083968..5a95ec9 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -214,6 +214,196 @@ static void amdgpu_command_submission_gfx(void) CU_ASSERT_EQUAL(r, 0); } +static void amdgpu_semaphore_test(void) +{ + amdgpu_context_handle context_handle[2]; + amdgpu_semaphore_handle sem; + amdgpu_bo_handle ib_result_handle[2]; + void *ib_result_cpu[2]; + uint64_t ib_result_mc_address[2]; + struct amdgpu_cs_request ibs_request[2] = {0}; + struct amdgpu_cs_ib_info ib_info[2] = {0}; + struct amdgpu_cs_fence fence_status = {0}; + uint32_t *ptr; + uint32_t expired; + amdgpu_bo_list_handle bo_list[2]; + amdgpu_va_handle va_handle[2]; + amdgpu_sem_handle sem_handle, sem_handle_import; + int fd; + int r, i; + + r = amdgpu_cs_create_semaphore(&sem); + CU_ASSERT_EQUAL(r, 0); + for (i = 0; i < 2; i++) { + r = amdgpu_cs_ctx_create(device_handle, &context_handle[i]); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, + AMDGPU_GEM_DOMAIN_GTT, 0, + &ib_result_handle[i], &ib_result_cpu[i], + &ib_result_mc_address[i], &va_handle[i]); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_get_bo_list(device_handle, ib_result_handle[i], + NULL, &bo_list[i]); + CU_ASSERT_EQUAL(r, 0); + } + + /* 1. same context different engine */ + ptr = ib_result_cpu[0]; + ptr[0] = SDMA_NOP; + ib_info[0].ib_mc_address = ib_result_mc_address[0]; + ib_info[0].size = 1; + + ibs_request[0].ip_type = AMDGPU_HW_IP_DMA; + ibs_request[0].number_of_ibs = 1; + ibs_request[0].ibs = &ib_info[0]; + ibs_request[0].resources = bo_list[0]; + ibs_request[0].fence_info.handle = NULL; + r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[0], 1); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_cs_signal_semaphore(context_handle[0], AMDGPU_HW_IP_DMA, 0, 0, sem); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_wait_semaphore(context_handle[0], AMDGPU_HW_IP_GFX, 0, 0, sem); + CU_ASSERT_EQUAL(r, 0); + ptr = ib_result_cpu[1]; + ptr[0] = GFX_COMPUTE_NOP; + ib_info[1].ib_mc_address = ib_result_mc_address[1]; + ib_info[1].size = 1; + + ibs_request[1].ip_type = AMDGPU_HW_IP_GFX; + ibs_request[1].number_of_ibs = 1; + ibs_request[1].ibs = &ib_info[1]; + ibs_request[1].resources = bo_list[1]; + ibs_request[1].fence_info.handle = NULL; + + r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[1], 1); + CU_ASSERT_EQUAL(r, 0); + + fence_status.context = context_handle[0]; + fence_status.ip_type = AMDGPU_HW_IP_GFX; + fence_status.ip_instance = 0; + fence_status.fence = ibs_request[1].seq_no; + r = amdgpu_cs_query_fence_status(&fence_status, + 500000000, 0, &expired); + CU_ASSERT_EQUAL(r, 0); + CU_ASSERT_EQUAL(expired, true); + + /* 2. same engine different context */ + ptr = ib_result_cpu[0]; + ptr[0] = GFX_COMPUTE_NOP; + ib_info[0].ib_mc_address = ib_result_mc_address[0]; + ib_info[0].size = 1; + + ibs_request[0].ip_type = AMDGPU_HW_IP_GFX; + ibs_request[0].number_of_ibs = 1; + ibs_request[0].ibs = &ib_info[0]; + ibs_request[0].resources = bo_list[0]; + ibs_request[0].fence_info.handle = NULL; + r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[0], 1); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_cs_signal_semaphore(context_handle[0], AMDGPU_HW_IP_GFX, 0, 0, sem); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_wait_semaphore(context_handle[1], AMDGPU_HW_IP_GFX, 0, 0, sem); + CU_ASSERT_EQUAL(r, 0); + ptr = ib_result_cpu[1]; + ptr[0] = GFX_COMPUTE_NOP; + ib_info[1].ib_mc_address = ib_result_mc_address[1]; + ib_info[1].size = 1; + + ibs_request[1].ip_type = AMDGPU_HW_IP_GFX; + ibs_request[1].number_of_ibs = 1; + ibs_request[1].ibs = &ib_info[1]; + ibs_request[1].resources = bo_list[1]; + ibs_request[1].fence_info.handle = NULL; + r = amdgpu_cs_submit(context_handle[1], 0,&ibs_request[1], 1); + + CU_ASSERT_EQUAL(r, 0); + + fence_status.context = context_handle[1]; + fence_status.ip_type = AMDGPU_HW_IP_GFX; + fence_status.ip_instance = 0; + fence_status.fence = ibs_request[1].seq_no; + r = amdgpu_cs_query_fence_status(&fence_status, + 500000000, 0, &expired); + CU_ASSERT_EQUAL(r, 0); + CU_ASSERT_EQUAL(expired, true); + + /* 3. export/import sem test */ + r = amdgpu_cs_create_sem(device_handle, &sem_handle); + CU_ASSERT_EQUAL(r, 0); + + ptr = ib_result_cpu[0]; + ptr[0] = SDMA_NOP; + ib_info[0].ib_mc_address = ib_result_mc_address[0]; + ib_info[0].size = 1; + + ibs_request[0].ip_type = AMDGPU_HW_IP_DMA; + ibs_request[0].number_of_ibs = 1; + ibs_request[0].ibs = &ib_info[0]; + ibs_request[0].resources = bo_list[0]; + ibs_request[0].fence_info.handle = NULL; + r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[0], 1); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_cs_signal_sem(device_handle, context_handle[0], AMDGPU_HW_IP_DMA, 0, 0, sem_handle); + CU_ASSERT_EQUAL(r, 0); + + // export the semaphore and import in different context to wait. + r = amdgpu_cs_export_sem(device_handle, sem_handle, &fd); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_import_sem(device_handle, fd, &sem_handle_import); + CU_ASSERT_EQUAL(r, 0); + close(fd); + r = amdgpu_cs_destroy_sem(device_handle, sem_handle); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_wait_sem(device_handle, context_handle[1], AMDGPU_HW_IP_GFX, 0, 0, sem_handle_import); + CU_ASSERT_EQUAL(r, 0); + ptr = ib_result_cpu[1]; + ptr[0] = GFX_COMPUTE_NOP; + ib_info[1].ib_mc_address = ib_result_mc_address[1]; + ib_info[1].size = 1; + + ibs_request[1].ip_type = AMDGPU_HW_IP_GFX; + ibs_request[1].number_of_ibs = 1; + ibs_request[1].ibs = &ib_info[1]; + ibs_request[1].resources = bo_list[1]; + ibs_request[1].fence_info.handle = NULL; + + r = amdgpu_cs_submit(context_handle[1], 0,&ibs_request[1], 1); + CU_ASSERT_EQUAL(r, 0); + + fence_status.context = context_handle[1]; + fence_status.ip_type = AMDGPU_HW_IP_GFX; + fence_status.ip_instance = 0; + fence_status.fence = ibs_request[1].seq_no; + r = amdgpu_cs_query_fence_status(&fence_status, + 500000000, 0, &expired); + CU_ASSERT_EQUAL(r, 0); + CU_ASSERT_EQUAL(expired, true); + + r = amdgpu_cs_destroy_sem(device_handle, sem_handle_import); + CU_ASSERT_EQUAL(r, 0); + + for (i = 0; i < 2; i++) { + r = amdgpu_bo_unmap_and_free(ib_result_handle[i], va_handle[i], + ib_result_mc_address[i], 4096); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_list_destroy(bo_list[i]); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_ctx_free(context_handle[i]); + CU_ASSERT_EQUAL(r, 0); + } + + r = amdgpu_cs_destroy_semaphore(sem); + CU_ASSERT_EQUAL(r, 0); +} + static void amdgpu_command_submission_compute(void) { amdgpu_context_handle context_handle; -- 1.9.1 --------------040601090507040301020506 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KYW1kLWdmeCBt YWlsaW5nIGxpc3QKYW1kLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5m cmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9hbWQtZ2Z4Cg== --------------040601090507040301020506-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?Q?Christian_K=c3=b6nig?= Subject: Re: Shared semaphores for amdgpu Date: Thu, 9 Mar 2017 08:38:44 +0100 Message-ID: References: <544E607D03B20249AA404517E498FC469A558B@exchange01.valvesoftware.com> <58B4D68E.5080606@amd.com> <58C0FD86.8040808@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <58C0FD86.8040808-5C7GfCeVMHo@public.gmane.org> List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: zhoucm1 , Dave Airlie Cc: "Mao, David" , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" , Andres Rodriguez , Andres Rodriguez , Dave Airlie , "Cui, Flora" , Pierre-Loup Griffais PiBJIGRvIHdvbmRlciBpZiB3ZSBuZWVkIHRoZSBzZXBhcmF0ZSBzZW0gc2lnbmFsL3dhaXQgaW50 ZXJmYWNlLCBJIHRoaW5rCj4gd2Ugc2hvdWxkIGp1c3QgYWRkCj4gc2VtYXBob3JlIGNodW5rcyB0 byB0aGUgQ1MgaW50ZXJmYWNlLgpZZWFoLCB0aGF0J3Mgd2hhdCBJJ3ZlIHNhaWQgYXMgd2VsbCBm cm9tIHRoZSB2ZXJ5IGZpcnN0IGJlZ2lubmluZy4KCkFub3RoZXIgcXVlc3Rpb24gaXMgaWYgd2Ug c2hvdWxkIHJlYWxseSBjcmVhdGUgYW5vdGhlciBpbXBsZW1lbnRhdGlvbiB0byAKc2hhcmUgc2Vt YXBob3JlcyBiZXR3ZWVuIHByb2Nlc3Nlcy4KCkluIG90aGVyIHdvcmRzIHB1dHRpbmcgdGhlIGN1 cnJlbnQgZmVuY2VzIGluc2lkZSB0aGUgc2VtYXBob3JlIGludG8gYSAKc3luY19maWxlIHdpdGgg dGhlIHNpZ25hbF9vbl9hbnkgYml0IHNldCB3b3VsZCBoYXZlIHByZXR0eSBtdWNoIHRoZSBzYW1l IAplZmZlY3QsIGV4Y2VwdCB0aGF0IHRoZSByZXN1bHRpbmcgb2JqZWN0IHRoZW4gaGFkIHRoZSBz eW5jX2ZpbGUgCnNlbWFudGljcyBmb3IgYWRkaW5nIG5ldyBmZW5jZXMgYW5kIGNhbiBiZSB1c2Vk IGluIHRoZSBhdG9taWMgSU9DVExzIGFzIAp3ZWxsLgoKUmVnYXJkcywKQ2hyaXN0aWFuLgoKQW0g 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cmVlIHdpdGggYWxsIHRoZXNlIGluIGl0LCBhbmQgc3RhcnRlZCBsb29raW5nIGludG8gdGhlIAo+ Pj4gaW50ZXJmYWNlLgo+Pj4KPj4+IEkgZG8gd29uZGVyIGlmIHdlIG5lZWQgdGhlIHNlcGFyYXRl IHNlbSBzaWduYWwvd2FpdCBpbnRlcmZhY2UsIEkgdGhpbmsKPj4+IHdlIHNob3VsZCBqdXN0IGFk ZAo+Pj4gc2VtYXBob3JlIGNodW5rcyB0byB0aGUgQ1MgaW50ZXJmYWNlLgo+Pj4KPj4+IEknbSBq dXN0IHBsYXlpbmcgYXJvdW5kIHdpdGggdGhpcyBub3cuCj4+Pgo+Pj4gRGF2ZS4KPgoKX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KYW1kLWdmeCBtYWlsaW5n IGxpc3QKYW1kLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVz a3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9hbWQtZ2Z4Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dave Airlie Subject: Re: Shared semaphores for amdgpu Date: Thu, 9 Mar 2017 18:15:25 +1000 Message-ID: References: <544E607D03B20249AA404517E498FC469A558B@exchange01.valvesoftware.com> <58B4D68E.5080606@amd.com> <58C0FD86.8040808@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: =?UTF-8?Q?Christian_K=C3=B6nig?= Cc: zhoucm1 , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" , "Mao, David" , Andres Rodriguez , Andres Rodriguez , Dave Airlie , "Cui, Flora" , Pierre-Loup Griffais T24gOSBNYXJjaCAyMDE3IGF0IDE3OjM4LCBDaHJpc3RpYW4gS8O2bmlnIDxjaHJpc3RpYW4ua29l bmlnQGFtZC5jb20+IHdyb3RlOgo+PiBJIGRvIHdvbmRlciBpZiB3ZSBuZWVkIHRoZSBzZXBhcmF0 ZSBzZW0gc2lnbmFsL3dhaXQgaW50ZXJmYWNlLCBJIHRoaW5rCj4+IHdlIHNob3VsZCBqdXN0IGFk ZAo+PiBzZW1hcGhvcmUgY2h1bmtzIHRvIHRoZSBDUyBpbnRlcmZhY2UuCj4KPiBZZWFoLCB0aGF0 J3Mgd2hhdCBJJ3ZlIHNhaWQgYXMgd2VsbCBmcm9tIHRoZSB2ZXJ5IGZpcnN0IGJlZ2lubmluZy4K Pgo+IEFub3RoZXIgcXVlc3Rpb24gaXMgaWYgd2Ugc2hvdWxkIHJlYWxseSBjcmVhdGUgYW5vdGhl ciBpbXBsZW1lbnRhdGlvbiB0bwo+IHNoYXJlIHNlbWFwaG9yZXMgYmV0d2VlbiBwcm9jZXNzZXMu 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Zy9tYWlsbWFuL2xpc3RpbmZvL2FtZC1nZngK From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?Q?Christian_K=c3=b6nig?= Subject: Re: Shared semaphores for amdgpu Date: Thu, 9 Mar 2017 10:12:40 +0100 Message-ID: <37118a87-28f2-c96d-18dc-a71292ea35d4@amd.com> References: <544E607D03B20249AA404517E498FC469A558B@exchange01.valvesoftware.com> <58B4D68E.5080606@amd.com> <58C0FD86.8040808@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: Dave Airlie Cc: zhoucm1 , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" , "Mao, David" , Andres Rodriguez , Andres Rodriguez , Dave Airlie , "Cui, Flora" , Pierre-Loup Griffais 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X19fX19fX19fX19fX19fX19fX19fCmFtZC1nZnggbWFpbGluZyBsaXN0CmFtZC1nZnhAbGlzdHMu ZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlz dGluZm8vYW1kLWdmeAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: zhoucm1 Subject: Re: Shared semaphores for amdgpu Date: Thu, 9 Mar 2017 17:43:02 +0800 Message-ID: <58C123A6.70209@amd.com> References: <544E607D03B20249AA404517E498FC469A558B@exchange01.valvesoftware.com> <58B4D68E.5080606@amd.com> <58C0FD86.8040808@amd.com> <37118a87-28f2-c96d-18dc-a71292ea35d4@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <37118a87-28f2-c96d-18dc-a71292ea35d4-5C7GfCeVMHo@public.gmane.org> List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: =?UTF-8?B?Q2hyaXN0aWFuIEvDtm5pZw==?= , Dave Airlie Cc: "Mao, David" , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" , Andres Rodriguez , Andres Rodriguez , Dave Airlie , "Cui, Flora" , Pierre-Loup Griffais CgpPbiAyMDE35bm0MDPmnIgwOeaXpSAxNzoxMiwgQ2hyaXN0aWFuIEvDtm5pZyB3cm90ZToKPiBB bSAwOS4wMy4yMDE3IHVtIDA5OjE1IHNjaHJpZWIgRGF2ZSBBaXJsaWU6Cj4+IE9uIDkgTWFyY2gg MjAxNyBhdCAxNzozOCwgQ2hyaXN0aWFuIEvDtm5pZyA8Y2hyaXN0aWFuLmtvZW5pZ0BhbWQuY29t PiAKPj4gd3JvdGU6Cj4+Pj4gSSBkbyB3b25kZXIgaWYgd2UgbmVlZCB0aGUgc2VwYXJhdGUgc2Vt IHNpZ25hbC93YWl0IGludGVyZmFjZSwgSSB0aGluawo+Pj4+IHdlIHNob3VsZCBqdXN0IGFkZAo+ Pj4+IHNlbWFwaG9yZSBjaHVua3MgdG8gdGhlIENTIGludGVyZmFjZS4KPj4+IFllYWgsIHRoYXQn cyB3aGF0IEkndmUgc2FpZCBhcyB3ZWxsIGZyb20gdGhlIHZlcnkgZmlyc3QgYmVnaW5uaW5nLgo+ Pj4KPj4+IEFub3RoZXIgcXVlc3Rpb24gaXMgaWYgd2Ugc2hvdWxkIHJlYWxseSBjcmVhdGUgYW5v dGhlciAKPj4+IGltcGxlbWVudGF0aW9uIHRvCj4+PiBzaGFyZSBzZW1hcGhvcmVzIGJldHdlZW4g cHJvY2Vzc2VzLgo+Pj4KPj4+IEluIG90aGVyIHdvcmRzIHB1dHRpbmcgdGhlIGN1cnJlbnQgZmVu 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c2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8v YW1kLWdmeAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?Q?Christian_K=c3=b6nig?= Subject: Re: Shared semaphores for amdgpu Date: Thu, 9 Mar 2017 11:31:15 +0100 Message-ID: References: <544E607D03B20249AA404517E498FC469A558B@exchange01.valvesoftware.com> <58B4D68E.5080606@amd.com> <58C0FD86.8040808@amd.com> <37118a87-28f2-c96d-18dc-a71292ea35d4@amd.com> <58C123A6.70209@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <58C123A6.70209-5C7GfCeVMHo@public.gmane.org> List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: zhoucm1 , =?UTF-8?Q?Christian_K=c3=b6nig?= , Dave Airlie Cc: "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" , "Mao, David" , Andres Rodriguez , Andres Rodriguez , Dave Airlie , "Cui, Flora" , Pierre-Loup Griffais QW0gMDkuMDMuMjAxNyB1bSAxMDo0MyBzY2hyaWViIHpob3VjbTE6Cj4KPgo+IE9uIDIwMTflubQw M+aciDA55pelIDE3OjEyLCBDaHJpc3RpYW4gS8O2bmlnIHdyb3RlOgo+PiBBbSAwOS4wMy4yMDE3 IHVtIDA5OjE1IHNjaHJpZWIgRGF2ZSBBaXJsaWU6Cj4+PiBPbiA5IE1hcmNoIDIwMTcgYXQgMTc6 MzgsIENocmlzdGlhbiBLw7ZuaWcgPGNocmlzdGlhbi5rb2VuaWdAYW1kLmNvbT4gCj4+PiB3cm90 ZToKPj4+Pj4gSSBkbyB3b25kZXIgaWYgd2UgbmVlZCB0aGUgc2VwYXJhdGUgc2VtIHNpZ25hbC93 YWl0IGludGVyZmFjZSwgSSAKPj4+Pj4gdGhpbmsKPj4+Pj4gd2Ugc2hvdWxkIGp1c3QgYWRkCj4+ Pj4+IHNlbWFwaG9yZSBjaHVua3MgdG8gdGhlIENTIGludGVyZmFjZS4KPj4+PiBZZWFoLCB0aGF0 J3Mgd2hhdCBJJ3ZlIHNhaWQgYXMgd2VsbCBmcm9tIHRoZSB2ZXJ5IGZpcnN0IGJlZ2lubmluZy4K Pj4+Pgo+Pj4+IEFub3RoZXIgcXVlc3Rpb24gaXMgaWYgd2Ugc2hvdWxkIHJlYWxseSBjcmVhdGUg YW5vdGhlciAKPj4+PiBpbXBsZW1lbnRhdGlvbiB0bwo+Pj4+IHNoYXJlIHNlbWFwaG9yZXMgYmV0 d2VlbiBwcm9jZXNzZXMuCj4+Pj4KPj4+PiBJbiBvdGhlciB3b3JkcyBwdXR0aW5nIHRoZSBjdXJy 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by9hbWQtZ2Z4CgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X18KYW1kLWdmeCBtYWlsaW5nIGxpc3QKYW1kLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0 cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9hbWQtZ2Z4Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dave Airlie Subject: Re: Shared semaphores for amdgpu Date: Fri, 10 Mar 2017 09:19:16 +1000 Message-ID: References: <544E607D03B20249AA404517E498FC469A558B@exchange01.valvesoftware.com> <58B4D68E.5080606@amd.com> <58C0FD86.8040808@amd.com> <37118a87-28f2-c96d-18dc-a71292ea35d4@amd.com> <58C123A6.70209@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: =?UTF-8?Q?Christian_K=C3=B6nig?= , dri-devel Cc: zhoucm1 , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" , "Mao, David" , Andres Rodriguez , Andres Rodriguez , Dave Airlie , "Cui, Flora" , =?UTF-8?Q?Christian_K=C3=B6nig?= , Pierre-Loup Griffais PiBDb21wbGV0ZWx5IGFncmVlLCBwcm9ibGVtIGhlcmUgaXMgdGhhdCB0aGlzIGlzbid0IGRvY3Vt ZW50ZWQgbGlrZSB0aGlzIGluCj4gdGhlIFZ1bGthbiBzcGVjaWZpY2F0aW9uIGFzIGZhciBhcyBJ IGtub3cuCgooSSdtIGFkZGluZyBkcmktZGV2ZWwsIHNpbmNlIEkgdGhpbmsgSW50ZWwgZm9sa3Mg aGF2ZSBsb29rZWQgaW50byBzb21lCm9mIHRoaXMgYWxyZWFkeSwKYW5kIHdlIG1pZ2h0IG5lZWQg dG8gbWFrZSBzb21lIGNvbW1vbiBmdW5jdGlvbmFsaXR5KS4KCiJUaGUgc2VtYXBob3JlIG11c3Qg YmUgc2lnbmFsZWQsIG9yIGhhdmUgYW4gYXNzb2NpYXRlZCBzZW1hcGhvcmUKc2lnbmFsIG9wZXJh dGlvbiB0aGF0IGlzCnBlbmRpbmcgZXhlY3V0aW9uLiIKClNvIEknbGwgdHJ5IGFuZCBzdW1tYXJp c2UgdGhlIHNlbWFudGljcyBvZiBzZW1hcGhvcmVzIHZzIGN1cnJlbnQgZmVuY2UgZmRzLgoKRm9y IHNoYXJlZCBzZW1hcGhvcmVzIHRoZXJlIGFyZSB0d28gZGVmaW5lZCBzZW1hbnRpY3M6IHRlbXBv cmFyeSBhbmQgcGVybWFuZW50LApJIHRoaW5rIHdlIHdvdWxkIG5lZWQgdG8gc3VwcG9ydCBib3Ro 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amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: Dave Airlie , =?UTF-8?Q?Christian_K=c3=b6nig?= , dri-devel Cc: zhoucm1 , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" , "Mao, David" , Andres Rodriguez , Andres Rodriguez , Dave Airlie , "Cui, Flora" , Pierre-Loup Griffais QW0gMTAuMDMuMjAxNyB1bSAwMDoxOSBzY2hyaWViIERhdmUgQWlybGllOgo+PiBDb21wbGV0ZWx5 IGFncmVlLCBwcm9ibGVtIGhlcmUgaXMgdGhhdCB0aGlzIGlzbid0IGRvY3VtZW50ZWQgbGlrZSB0 aGlzIGluCj4+IHRoZSBWdWxrYW4gc3BlY2lmaWNhdGlvbiBhcyBmYXIgYXMgSSBrbm93Lgo+IChJ J20gYWRkaW5nIGRyaS1kZXZlbCwgc2luY2UgSSB0aGluayBJbnRlbCBmb2xrcyBoYXZlIGxvb2tl ZCBpbnRvIHNvbWUKPiBvZiB0aGlzIGFscmVhZHksCj4gYW5kIHdlIG1pZ2h0IG5lZWQgdG8gbWFr ZSBzb21lIGNvbW1vbiBmdW5jdGlvbmFsaXR5KS4KPgo+ICJUaGUgc2VtYXBob3JlIG11c3QgYmUg c2lnbmFsZWQsIG9yIGhhdmUgYW4gYXNzb2NpYXRlZCBzZW1hcGhvcmUKPiBzaWduYWwgb3BlcmF0 aW9uIHRoYXQgaXMKPiBwZW5kaW5nIGV4ZWN1dGlvbi4iCj4KPiBTbyBJJ2xsIHRyeSBhbmQgc3Vt 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text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <85322d42-e585-659d-6f98-fc5baf0d6b14-5C7GfCeVMHo@public.gmane.org> List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: =?UTF-8?Q?Christian_K=C3=B6nig?= Cc: zhoucm1 , "Mao, David" , dri-devel , Andres Rodriguez , =?UTF-8?Q?Christian_K=C3=B6nig?= , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" , Dave Airlie , "Cui, Flora" , Pierre-Loup Griffais , Andres Rodriguez Pgo+IEFzIGZhciBhcyBJIGNhbiBzZWUgdGhlIG9ubHkgZnVuY3Rpb25hbGl0eSB3ZSBhcmUgbWlz c2luZyBoZXJlIGlzOgo+Cj4gdm9pZCBzeW5jX2ZpbGVfc2lnbmFsKHN0cnVjdCBzeW5jX2ZpbGUg KnN5bmNfZmlsZSwgc3RydWN0IGRtYV9mZW5jZSAqZmVuY2UpCj4gewo+ICAgICBkbWFfZmVuY2Vf cHV0KHN5bmNfZmlsZS0+ZmVuY2UpOwo+ICAgICBzeW5jX2ZpbGUtPmZlbmNlID0gZmVuY2U7Cj4g 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L2xpc3RpbmZvL2FtZC1nZngK From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dave Airlie Subject: Re: Shared semaphores for amdgpu Date: Fri, 10 Mar 2017 14:27:11 +1000 Message-ID: References: <544E607D03B20249AA404517E498FC469A558B@exchange01.valvesoftware.com> <58B4D68E.5080606@amd.com> <58C0FD86.8040808@amd.com> <37118a87-28f2-c96d-18dc-a71292ea35d4@amd.com> <58C123A6.70209@amd.com> <85322d42-e585-659d-6f98-fc5baf0d6b14@amd.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary=001a113e2f9e93a8c2054a58c63a Return-path: In-Reply-To: List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: =?UTF-8?Q?Christian_K=C3=B6nig?= Cc: zhoucm1 , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" , "Mao, David" , Andres Rodriguez , =?UTF-8?Q?Christian_K=C3=B6nig?= , Andres Rodriguez , Dave Airlie , "Cui, Flora" , Pierre-Loup Griffais --001a113e2f9e93a8c2054a58c63a Content-Type: text/plain; charset=UTF-8 On 10 March 2017 at 13:25, Dave Airlie wrote: >> >> As far as I can see the only functionality we are missing here is: >> >> void sync_file_signal(struct sync_file *sync_file, struct dma_fence *fence) >> { >> dma_fence_put(sync_file->fence); >> sync_file->fence = fence; >> } >> >> We probably should do this atomically, but that is only a matter of taking >> locks/atomic pointer operation. >> >> The waiting is done using the normal sync_file_get_fence() function. >> >> The rest is David's patch to import/export the fd handle into a local idr >> based handle. > > Are you suggesting we start keeping track of sync_file objects in a local idr? > > As currently they are only tracked as files, which is probably not what we want > for every unshared semaphore, or are you thinking more that the amdgpu local > sem should be just storing a sync_file pointer, rather than what it does now. Okay here's a first pass at what I think you mean, it's missing things, but the idea should be what you said. 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<58C123A6.70209@amd.com> <85322d42-e585-659d-6f98-fc5baf0d6b14@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: =?UTF-8?Q?Christian_K=C3=B6nig?= Cc: zhoucm1 , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" , "Mao, David" , Andres Rodriguez , =?UTF-8?Q?Christian_K=C3=B6nig?= , Andres Rodriguez , Dave Airlie , "Cui, Flora" , Pierre-Loup Griffais T24gMTAgTWFyY2ggMjAxNyBhdCAxNDoyNywgRGF2ZSBBaXJsaWUgPGFpcmxpZWRAZ21haWwuY29t PiB3cm90ZToKPiBPbiAxMCBNYXJjaCAyMDE3IGF0IDEzOjI1LCBEYXZlIEFpcmxpZSA8YWlybGll ZEBnbWFpbC5jb20+IHdyb3RlOgo+Pj4KPj4+IEFzIGZhciBhcyBJIGNhbiBzZWUgdGhlIG9ubHkg ZnVuY3Rpb25hbGl0eSB3ZSBhcmUgbWlzc2luZyBoZXJlIGlzOgo+Pj4KPj4+IHZvaWQgc3luY19m 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