diff for duplicates of <58D250BC.4040609@rock-chips.com> diff --git a/a/content_digest b/N1/content_digest index be0dfde..4a6e4cb 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -6,42 +6,42 @@ "Date\0Wed, 22 Mar 2017 18:23:56 +0800\0" "To\0Heiko St\303\274bner <heiko@sntech.de>" " cl@rock-chips.com\0" - "Cc\0mark.rutland@arm.com" - wsa@the-dreams.de - linux-iio@vger.kernel.org - catalin.marinas@arm.com - shawn.lin@rock-chips.com - will.deacon@arm.com - kever.yang@rock-chips.com - dianders@chromium.org - yamada.masahiro@socionext.com - tony.xie@rock-chips.com - linux-i2c@vger.kernel.org - pmeerw@pmeerw.net - lars@metafoo.de + "Cc\0robh+dt@kernel.org" + mark.rutland@arm.com zhengxing@rock-chips.com - khilman@baylibre.com - linux-rockchip@lists.infradead.org + andy.yan@rock-chips.com jay.xu@rock-chips.com - wxt@rock-chips.com - huangtao@rock-chips.com - devicetree@vger.kernel.org - paweljarosz3691@gmail.com - arnd@arndb.de - yhx@rock-chips.com - knaack.h@gmx.de - robh+dt@kernel.org matthias.bgg@gmail.com - rocky.hao@rock-chips.com + paweljarosz3691@gmail.com + devicetree@vger.kernel.org linux-arm-kernel@lists.infradead.org + linux-rockchip@lists.infradead.org linux-kernel@vger.kernel.org + wsa@the-dreams.de + linux-i2c@vger.kernel.org + jic23@kernel.org + knaack.h@gmx.de + lars@metafoo.de + pmeerw@pmeerw.net + wxt@rock-chips.com david.wu@rock-chips.com - fabio.estevam@nxp.com - andy.yan@rock-chips.com + linux-iio@vger.kernel.org + shawn.lin@rock-chips.com akpm@linux-foundation.org - shawnguo@kernel.org + dianders@chromium.org + yamada.masahiro@socionext.com + catalin.marinas@arm.com + will.deacon@arm.com afaerber@suse.de - " jic23@kernel.org\0" + shawnguo@kernel.org + khilman@baylibre.com + arnd@arndb.de + fabio.estevam@nxp.com + kever.yang@rock-chips.com + tony.xie@rock-chips.com + huangtao@rock-chips.com + yhx@rock-chips.com + " rocky.hao@rock-chips.com\0" "\00:1\0" "b\0" "\n" @@ -560,4 +560,4 @@ ">\n" > -c539a06a5899c6cd7886e18286d98f13eac27645a58b8b71326a161145e73ce0 +13f76bb0dcfe3063a1aa3ede36886d3a47f5894c60c0cf63ee3641cab302d9ff
diff --git a/a/1.txt b/N2/1.txt index f288844..0aa8593 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,9 +1,9 @@ -On 03/21/2017 04:55 PM, Heiko Stübner wrote: +On 03/21/2017 04:55 PM, Heiko St?bner wrote: > Hi, > -> Am Donnerstag, 16. März 2017, 21:17:22 CET schrieb cl@rock-chips.com: +> Am Donnerstag, 16. M?rz 2017, 21:17:22 CET schrieb cl at rock-chips.com: >> From: Liang Chen <cl@rock-chips.com> >> >> This patch adds core dtsi file for Rockchip RK3328 SoCs. @@ -94,26 +94,26 @@ On 03/21/2017 04:55 PM, Heiko Stübner wrote: > >> + #size-cells = <0>; >> + ->> + cpu0: cpu@0 { +>> + cpu0: cpu at 0 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53", "arm,armv8"; >> + reg = <0x0 0x0>; >> + enable-method = "psci"; >> + clocks = <&cru ARMCLK>; >> + }; ->> + cpu1: cpu@1 { +>> + cpu1: cpu at 1 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53", "arm,armv8"; >> + reg = <0x0 0x1>; >> + enable-method = "psci"; >> + }; ->> + cpu2: cpu@2 { +>> + cpu2: cpu at 2 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53", "arm,armv8"; >> + reg = <0x0 0x2>; >> + enable-method = "psci"; >> + }; ->> + cpu3: cpu@3 { +>> + cpu3: cpu at 3 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53", "arm,armv8"; >> + reg = <0x0 0x3>; @@ -157,7 +157,7 @@ On 03/21/2017 04:55 PM, Heiko Stübner wrote: > > [...] > ->> + wdt: watchdog@ff1a0000 { +>> + wdt: watchdog at ff1a0000 { >> + compatible = "snps,dw-wdt"; >> + reg = <0x0 0xff1a0000 0x0 0x100>; >> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; @@ -173,7 +173,7 @@ On 03/21/2017 04:55 PM, Heiko Stübner wrote: >> + #size-cells = <2>; >> + ranges; >> + ->> + dmac: dmac@ff1f0000 { +>> + dmac: dmac at ff1f0000 { >> + compatible = "arm,pl330", "arm,primecell"; >> + reg = <0x0 0xff1f0000 0x0 0x4000>; >> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, @@ -184,7 +184,7 @@ On 03/21/2017 04:55 PM, Heiko Stübner wrote: >> + }; >> + }; >> + ->> + saradc: saradc@ff280000 { +>> + saradc: saradc at ff280000 { >> + compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; >> + reg = <0x0 0xff280000 0x0 0x100>; >> + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; @@ -196,7 +196,7 @@ On 03/21/2017 04:55 PM, Heiko Stübner wrote: >> + status = "disabled"; >> + }; >> + ->> + cru: clock-controller@ff440000 { +>> + cru: clock-controller at ff440000 { >> + compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; >> + reg = <0x0 0xff440000 0x0 0x1000>; >> + rockchip,grf = <&grf>; @@ -275,10 +275,10 @@ After pll init, others clk init freq can inited in their device node. >> + <32768>, <32768>; >> + }; >> + ->> + gmac2io: eth@ff540000 { +>> + gmac2io: eth at ff540000 { > > phandle should be gmac instead? -> Node name, ethernet@ff540000 +> Node name, ethernet at ff540000 > >> + compatible = "rockchip,rk3328-gmac"; >> + reg = <0x0 0xff540000 0x0 0x10000>; @@ -298,7 +298,7 @@ After pll init, others clk init freq can inited in their device node. >> + status = "disabled"; >> + }; >> + ->> + gic: interrupt-controller@ff811000 { +>> + gic: interrupt-controller at ff811000 { >> + compatible = "arm,gic-400"; >> + #interrupt-cells = <3>; >> + #address-cells = <0>; @@ -318,7 +318,7 @@ After pll init, others clk init freq can inited in their device node. >> + #size-cells = <2>; >> + ranges; >> + ->> + gpio0: gpio0@ff210000 { +>> + gpio0: gpio0 at ff210000 { >> + compatible = "rockchip,gpio-bank"; >> + reg = <0x0 0xff210000 0x0 0x100>; >> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; @@ -331,7 +331,7 @@ After pll init, others clk init freq can inited in their device node. >> + #interrupt-cells = <2>; >> + }; >> + ->> + gpio1: gpio1@ff220000 { +>> + gpio1: gpio1 at ff220000 { >> + compatible = "rockchip,gpio-bank"; >> + reg = <0x0 0xff220000 0x0 0x100>; >> + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; @@ -344,7 +344,7 @@ After pll init, others clk init freq can inited in their device node. >> + #interrupt-cells = <2>; >> + }; >> + ->> + gpio2: gpio2@ff230000 { +>> + gpio2: gpio2 at ff230000 { >> + compatible = "rockchip,gpio-bank"; >> + reg = <0x0 0xff230000 0x0 0x100>; >> + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; @@ -357,7 +357,7 @@ After pll init, others clk init freq can inited in their device node. >> + #interrupt-cells = <2>; >> + }; >> + ->> + gpio3: gpio3@ff240000 { +>> + gpio3: gpio3 at ff240000 { >> + compatible = "rockchip,gpio-bank"; >> + reg = <0x0 0xff240000 0x0 0x100>; >> + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; diff --git a/a/content_digest b/N2/content_digest index be0dfde..363d459 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,55 +1,18 @@ "ref\01489670244-13328-1-git-send-email-cl@rock-chips.com\0" "ref\01489670244-13328-5-git-send-email-cl@rock-chips.com\0" "ref\014610453.rKm3MBREMz@diego\0" - "From\0Elaine Zhang <zhangqing@rock-chips.com>\0" - "Subject\0Re: [PATCH v2 4/6] arm64: dts: rockchip: add core dtsi file for RK3328 SoCs\0" + "From\0zhangqing@rock-chips.com (Elaine Zhang)\0" + "Subject\0[PATCH v2 4/6] arm64: dts: rockchip: add core dtsi file for RK3328 SoCs\0" "Date\0Wed, 22 Mar 2017 18:23:56 +0800\0" - "To\0Heiko St\303\274bner <heiko@sntech.de>" - " cl@rock-chips.com\0" - "Cc\0mark.rutland@arm.com" - wsa@the-dreams.de - linux-iio@vger.kernel.org - catalin.marinas@arm.com - shawn.lin@rock-chips.com - will.deacon@arm.com - kever.yang@rock-chips.com - dianders@chromium.org - yamada.masahiro@socionext.com - tony.xie@rock-chips.com - linux-i2c@vger.kernel.org - pmeerw@pmeerw.net - lars@metafoo.de - zhengxing@rock-chips.com - khilman@baylibre.com - linux-rockchip@lists.infradead.org - jay.xu@rock-chips.com - wxt@rock-chips.com - huangtao@rock-chips.com - devicetree@vger.kernel.org - paweljarosz3691@gmail.com - arnd@arndb.de - yhx@rock-chips.com - knaack.h@gmx.de - robh+dt@kernel.org - matthias.bgg@gmail.com - rocky.hao@rock-chips.com - linux-arm-kernel@lists.infradead.org - linux-kernel@vger.kernel.org - david.wu@rock-chips.com - fabio.estevam@nxp.com - andy.yan@rock-chips.com - akpm@linux-foundation.org - shawnguo@kernel.org - afaerber@suse.de - " jic23@kernel.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "\n" "\n" - "On 03/21/2017 04:55 PM, Heiko St\303\274bner wrote:\n" + "On 03/21/2017 04:55 PM, Heiko St?bner wrote:\n" "> Hi,\n" ">\n" - "> Am Donnerstag, 16. M\303\244rz 2017, 21:17:22 CET schrieb cl@rock-chips.com:\n" + "> Am Donnerstag, 16. M?rz 2017, 21:17:22 CET schrieb cl at rock-chips.com:\n" ">> From: Liang Chen <cl@rock-chips.com>\n" ">>\n" ">> This patch adds core dtsi file for Rockchip RK3328 SoCs.\n" @@ -140,26 +103,26 @@ ">\n" ">> +\t\t#size-cells = <0>;\n" ">> +\n" - ">> +\t\tcpu0: cpu@0 {\n" + ">> +\t\tcpu0: cpu at 0 {\n" ">> +\t\t\tdevice_type = \"cpu\";\n" ">> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" ">> +\t\t\treg = <0x0 0x0>;\n" ">> +\t\t\tenable-method = \"psci\";\n" ">> +\t\t\tclocks = <&cru ARMCLK>;\n" ">> +\t\t};\n" - ">> +\t\tcpu1: cpu@1 {\n" + ">> +\t\tcpu1: cpu at 1 {\n" ">> +\t\t\tdevice_type = \"cpu\";\n" ">> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" ">> +\t\t\treg = <0x0 0x1>;\n" ">> +\t\t\tenable-method = \"psci\";\n" ">> +\t\t};\n" - ">> +\t\tcpu2: cpu@2 {\n" + ">> +\t\tcpu2: cpu at 2 {\n" ">> +\t\t\tdevice_type = \"cpu\";\n" ">> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" ">> +\t\t\treg = <0x0 0x2>;\n" ">> +\t\t\tenable-method = \"psci\";\n" ">> +\t\t};\n" - ">> +\t\tcpu3: cpu@3 {\n" + ">> +\t\tcpu3: cpu at 3 {\n" ">> +\t\t\tdevice_type = \"cpu\";\n" ">> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" ">> +\t\t\treg = <0x0 0x3>;\n" @@ -203,7 +166,7 @@ ">\n" "> [...]\n" ">\n" - ">> +\twdt: watchdog@ff1a0000 {\n" + ">> +\twdt: watchdog at ff1a0000 {\n" ">> +\t\tcompatible = \"snps,dw-wdt\";\n" ">> +\t\treg = <0x0 0xff1a0000 0x0 0x100>;\n" ">> +\t\tinterrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -219,7 +182,7 @@ ">> +\t\t#size-cells = <2>;\n" ">> +\t\tranges;\n" ">> +\n" - ">> +\t\tdmac: dmac@ff1f0000 {\n" + ">> +\t\tdmac: dmac at ff1f0000 {\n" ">> +\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n" ">> +\t\t\treg = <0x0 0xff1f0000 0x0 0x4000>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -230,7 +193,7 @@ ">> +\t\t};\n" ">> +\t};\n" ">> +\n" - ">> +\tsaradc: saradc@ff280000 {\n" + ">> +\tsaradc: saradc at ff280000 {\n" ">> +\t\tcompatible = \"rockchip,rk3328-saradc\", \"rockchip,rk3399-saradc\";\n" ">> +\t\treg = <0x0 0xff280000 0x0 0x100>;\n" ">> +\t\tinterrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -242,7 +205,7 @@ ">> +\t\tstatus = \"disabled\";\n" ">> +\t};\n" ">> +\n" - ">> +\tcru: clock-controller@ff440000 {\n" + ">> +\tcru: clock-controller at ff440000 {\n" ">> +\t\tcompatible = \"rockchip,rk3328-cru\", \"rockchip,cru\", \"syscon\";\n" ">> +\t\treg = <0x0 0xff440000 0x0 0x1000>;\n" ">> +\t\trockchip,grf = <&grf>;\n" @@ -321,10 +284,10 @@ ">> +\t\t\t<32768>, <32768>;\n" ">> +\t};\n" ">> +\n" - ">> +\tgmac2io: eth@ff540000 {\n" + ">> +\tgmac2io: eth at ff540000 {\n" ">\n" "> phandle should be gmac instead?\n" - "> Node name, ethernet@ff540000\n" + "> Node name, ethernet at ff540000\n" ">\n" ">> +\t\tcompatible = \"rockchip,rk3328-gmac\";\n" ">> +\t\treg = <0x0 0xff540000 0x0 0x10000>;\n" @@ -344,7 +307,7 @@ ">> +\t\tstatus = \"disabled\";\n" ">> +\t};\n" ">> +\n" - ">> +\tgic: interrupt-controller@ff811000 {\n" + ">> +\tgic: interrupt-controller at ff811000 {\n" ">> +\t\tcompatible = \"arm,gic-400\";\n" ">> +\t\t#interrupt-cells = <3>;\n" ">> +\t\t#address-cells = <0>;\n" @@ -364,7 +327,7 @@ ">> +\t\t#size-cells = <2>;\n" ">> +\t\tranges;\n" ">> +\n" - ">> +\t\tgpio0: gpio0@ff210000 {\n" + ">> +\t\tgpio0: gpio0 at ff210000 {\n" ">> +\t\t\tcompatible = \"rockchip,gpio-bank\";\n" ">> +\t\t\treg = <0x0 0xff210000 0x0 0x100>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -377,7 +340,7 @@ ">> +\t\t\t#interrupt-cells = <2>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tgpio1: gpio1@ff220000 {\n" + ">> +\t\tgpio1: gpio1 at ff220000 {\n" ">> +\t\t\tcompatible = \"rockchip,gpio-bank\";\n" ">> +\t\t\treg = <0x0 0xff220000 0x0 0x100>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -390,7 +353,7 @@ ">> +\t\t\t#interrupt-cells = <2>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tgpio2: gpio2@ff230000 {\n" + ">> +\t\tgpio2: gpio2 at ff230000 {\n" ">> +\t\t\tcompatible = \"rockchip,gpio-bank\";\n" ">> +\t\t\treg = <0x0 0xff230000 0x0 0x100>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -403,7 +366,7 @@ ">> +\t\t\t#interrupt-cells = <2>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tgpio3: gpio3@ff240000 {\n" + ">> +\t\tgpio3: gpio3 at ff240000 {\n" ">> +\t\t\tcompatible = \"rockchip,gpio-bank\";\n" ">> +\t\t\treg = <0x0 0xff240000 0x0 0x100>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -560,4 +523,4 @@ ">\n" > -c539a06a5899c6cd7886e18286d98f13eac27645a58b8b71326a161145e73ce0 +9c93ff02416931c00a270ddb90786550ffd876a92edf824a6c85541552de9861
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.