diff for duplicates of <58E4516D.4000805@rock-chips.com> diff --git a/a/content_digest b/N1/content_digest index 0f96579..ac669fb 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -38,7 +38,10 @@ arnd@arndb.de fabio.estevam@nxp.com kever.yang@rock-chips.com - " tony.xie@rock-chips.com\0" + tony.xie@rock-chips.com + huangtao@rock-chips.com + yhx@rock-chips.com + " rocky.hao@rock-chips.com\0" "\00:1\0" "b\0" "\n" @@ -88,4 +91,4 @@ ">\n" > -2f69a9f829c881b8ee55b4edd9b917f2204467525ad827f2bc0325bc77a33f6d +5b4a650dffddf2d2748f296d05c78d696493395b84c498e95071e88cbb260530
diff --git a/a/1.txt b/N2/1.txt index 84dd2e4..cbcfaeb 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,7 +1,7 @@ On 04/05/2017 12:04 AM, Heiko Stuebner wrote: -> Am Montag, 27. März 2017, 17:40:48 CEST schrieb cl@rock-chips.com: +> Am Montag, 27. M?rz 2017, 17:40:48 CEST schrieb cl at rock-chips.com: >> From: Liang Chen <cl@rock-chips.com> >> >> This patch adds core dtsi file for Rockchip RK3328 SoCs. @@ -34,10 +34,10 @@ please see the TRM in CRU: 1.4 Function Description /........./ To maximize the flexibility, some of clocks can select divider source -from 5 PLLs. (Note: It’s +from 5 PLLs. (Note: It?s recommended to use NEW PLL instead of ARM PLL as arm clock source, because NEW PLL is -near to ARM. And it’s jitter is better than ARM PLL). +near to ARM. And it?s jitter is better than ARM PLL). > > Heiko diff --git a/a/content_digest b/N2/content_digest index 0f96579..877341a 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,50 +1,16 @@ "ref\01490607650-18650-1-git-send-email-cl@rock-chips.com\0" "ref\01490607650-18650-4-git-send-email-cl@rock-chips.com\0" "ref\06636047.jL6XHNkknt@phil\0" - "From\0Elaine Zhang <zhangqing@rock-chips.com>\0" - "Subject\0Re: [PATCH v4 4/6] arm64: dts: rockchip: add core dtsi file for RK3328 SoCs\0" + "From\0zhangqing@rock-chips.com (Elaine Zhang)\0" + "Subject\0[PATCH v4 4/6] arm64: dts: rockchip: add core dtsi file for RK3328 SoCs\0" "Date\0Wed, 05 Apr 2017 10:07:41 +0800\0" - "To\0Heiko Stuebner <heiko@sntech.de>" - " cl@rock-chips.com\0" - "Cc\0robh+dt@kernel.org" - mark.rutland@arm.com - zhengxing@rock-chips.com - andy.yan@rock-chips.com - jay.xu@rock-chips.com - matthias.bgg@gmail.com - paweljarosz3691@gmail.com - devicetree@vger.kernel.org - linux-arm-kernel@lists.infradead.org - linux-rockchip@lists.infradead.org - linux-kernel@vger.kernel.org - wsa@the-dreams.de - linux-i2c@vger.kernel.org - jic23@kernel.org - knaack.h@gmx.de - lars@metafoo.de - pmeerw@pmeerw.net - wxt@rock-chips.com - david.wu@rock-chips.com - linux-iio@vger.kernel.org - shawn.lin@rock-chips.com - akpm@linux-foundation.org - dianders@chromium.org - yamada.masahiro@socionext.com - catalin.marinas@arm.com - will.deacon@arm.com - afaerber@suse.de - shawnguo@kernel.org - khilman@baylibre.com - arnd@arndb.de - fabio.estevam@nxp.com - kever.yang@rock-chips.com - " tony.xie@rock-chips.com\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "\n" "\n" "On 04/05/2017 12:04 AM, Heiko Stuebner wrote:\n" - "> Am Montag, 27. M\303\244rz 2017, 17:40:48 CEST schrieb cl@rock-chips.com:\n" + "> Am Montag, 27. M?rz 2017, 17:40:48 CEST schrieb cl at rock-chips.com:\n" ">> From: Liang Chen <cl@rock-chips.com>\n" ">>\n" ">> This patch adds core dtsi file for Rockchip RK3328 SoCs.\n" @@ -77,10 +43,10 @@ "1.4 Function Description\n" "/........./\n" "To maximize the flexibility, some of clocks can select divider source \n" - "from 5 PLLs. (Note: It\342\200\231s\n" + "from 5 PLLs. (Note: It?s\n" "recommended to use NEW PLL instead of ARM PLL as arm clock source, \n" "because NEW PLL is\n" - "near to ARM. And it\342\200\231s jitter is better than ARM PLL).\n" + "near to ARM. And it?s jitter is better than ARM PLL).\n" "\n" ">\n" "> Heiko\n" @@ -88,4 +54,4 @@ ">\n" > -2f69a9f829c881b8ee55b4edd9b917f2204467525ad827f2bc0325bc77a33f6d +43d9b3474879747fe292ffa8ee26a49772d88cf3a7a369daf78f817d5422a61b
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