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Tue, 08 Nov 2022 09:37:20 -0800 (PST) Message-ID: <58d55016-afc7-e560-32cf-8228794b5752@gmail.com> Date: Tue, 8 Nov 2022 18:37:19 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.1 Subject: Re: [PATCH v28 05/11] soc: mediatek: refine code to use mtk_mmsys_update_bits API Content-Language: en-US To: "Nancy.Lin" , Rob Herring , Chun-Kuang Hu , Philipp Zabel , wim@linux-watchdog.org, AngeloGioacchino Del Regno , linux@roeck-us.net, nfraprado@collabora.com Cc: David Airlie , Daniel Vetter , Nathan Chancellor , Nick Desaulniers , "jason-jh . lin" , Yongqiang Niu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org, llvm@lists.linux.dev, singo.chang@mediatek.com, Project_Global_Chrome_Upstream_Group@mediatek.com References: <20221107072243.15748-1-nancy.lin@mediatek.com> <20221107072243.15748-6-nancy.lin@mediatek.com> From: Matthias Brugger In-Reply-To: <20221107072243.15748-6-nancy.lin@mediatek.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221108_093725_859737_98367E45 X-CRM114-Status: GOOD ( 23.14 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On 07/11/2022 08:22, Nancy.Lin wrote: > Simplify code for update mmsys reg. > > Signed-off-by: Nancy.Lin > Reviewed-by: AngeloGioacchino Del Regno > Reviewed-by: CK Hu > Tested-by: AngeloGioacchino Del Regno > Tested-by: Bo-Chen Chen > Reviewed-by: Nícolas F. R. A. Prado > --- > drivers/soc/mediatek/mtk-mmsys.c | 45 ++++++++++++-------------------- > 1 file changed, 16 insertions(+), 29 deletions(-) > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > index 9a327eb5d9d7..73c8bd27e6ae 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -99,22 +99,27 @@ struct mtk_mmsys { > struct reset_controller_dev rcdev; > }; > > +static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val) > +{ > + u32 tmp; > + > + tmp = readl_relaxed(mmsys->regs + offset); > + tmp = (tmp & ~mask) | (val & mask); I'm not sure about the change in the implementation of mtk_mmsys_update_bits(). Nicolas tried to explain it to me on IRC but I wasn't totally convincing. As we have to go for at least another round of this patches, I'd like to get a clear understanding while it is needed that val bits are set to 1 in the mask. Regards, Matthias > + writel_relaxed(tmp, mmsys->regs + offset); > +} > + > void mtk_mmsys_ddp_connect(struct device *dev, > enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next) > { > struct mtk_mmsys *mmsys = dev_get_drvdata(dev); > const struct mtk_mmsys_routes *routes = mmsys->data->routes; > - u32 reg; > int i; > > for (i = 0; i < mmsys->data->num_routes; i++) > - if (cur == routes[i].from_comp && next == routes[i].to_comp) { > - reg = readl_relaxed(mmsys->regs + routes[i].addr); > - reg &= ~routes[i].mask; > - reg |= routes[i].val; > - writel_relaxed(reg, mmsys->regs + routes[i].addr); > - } > + if (cur == routes[i].from_comp && next == routes[i].to_comp) > + mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, > + routes[i].val); > } > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); > > @@ -124,27 +129,14 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > { > struct mtk_mmsys *mmsys = dev_get_drvdata(dev); > const struct mtk_mmsys_routes *routes = mmsys->data->routes; > - u32 reg; > int i; > > for (i = 0; i < mmsys->data->num_routes; i++) > - if (cur == routes[i].from_comp && next == routes[i].to_comp) { > - reg = readl_relaxed(mmsys->regs + routes[i].addr); > - reg &= ~routes[i].mask; > - writel_relaxed(reg, mmsys->regs + routes[i].addr); > - } > + if (cur == routes[i].from_comp && next == routes[i].to_comp) > + mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, 0); > } > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); > > -static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val) > -{ > - u32 tmp; > - > - tmp = readl_relaxed(mmsys->regs + offset); > - tmp = (tmp & ~mask) | val; > - writel_relaxed(tmp, mmsys->regs + offset); > -} > - > void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val) > { > if (val) > @@ -161,18 +153,13 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l > { > struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev); > unsigned long flags; > - u32 reg; > > spin_lock_irqsave(&mmsys->lock, flags); > > - reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset); > - > if (assert) > - reg &= ~BIT(id); > + mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), 0); > else > - reg |= BIT(id); > - > - writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset); > + mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), BIT(id)); > > spin_unlock_irqrestore(&mmsys->lock, flags); > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3A0EAC433FE for ; Tue, 8 Nov 2022 17:38:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; 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([37.222.251.204]) by smtp.gmail.com with ESMTPSA id v18-20020a5d4b12000000b002365f326037sm13165230wrq.63.2022.11.08.09.37.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 08 Nov 2022 09:37:20 -0800 (PST) Message-ID: <58d55016-afc7-e560-32cf-8228794b5752@gmail.com> Date: Tue, 8 Nov 2022 18:37:19 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.1 Subject: Re: [PATCH v28 05/11] soc: mediatek: refine code to use mtk_mmsys_update_bits API Content-Language: en-US To: "Nancy.Lin" , Rob Herring , Chun-Kuang Hu , Philipp Zabel , wim@linux-watchdog.org, AngeloGioacchino Del Regno , linux@roeck-us.net, nfraprado@collabora.com Cc: David Airlie , Daniel Vetter , Nathan Chancellor , Nick Desaulniers , "jason-jh . lin" , Yongqiang Niu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org, llvm@lists.linux.dev, singo.chang@mediatek.com, Project_Global_Chrome_Upstream_Group@mediatek.com References: <20221107072243.15748-1-nancy.lin@mediatek.com> <20221107072243.15748-6-nancy.lin@mediatek.com> From: Matthias Brugger In-Reply-To: <20221107072243.15748-6-nancy.lin@mediatek.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221108_093725_859737_98367E45 X-CRM114-Status: GOOD ( 23.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: base64 Content-Type: text/plain; charset="utf-8"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org CgpPbiAwNy8xMS8yMDIyIDA4OjIyLCBOYW5jeS5MaW4gd3JvdGU6Cj4gU2ltcGxpZnkgY29kZSBm b3IgdXBkYXRlICBtbXN5cyByZWcuCj4gCj4gU2lnbmVkLW9mZi1ieTogTmFuY3kuTGluIDxuYW5j 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<20221107072243.15748-1-nancy.lin@mediatek.com> <20221107072243.15748-6-nancy.lin@mediatek.com> From: Matthias Brugger In-Reply-To: <20221107072243.15748-6-nancy.lin@mediatek.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Project_Global_Chrome_Upstream_Group@mediatek.com, David Airlie , "jason-jh . lin" , singo.chang@mediatek.com, llvm@lists.linux.dev, Nick Desaulniers , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Nathan Chancellor , linux-mediatek@lists.infradead.org, Yongqiang Niu , linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 07/11/2022 08:22, Nancy.Lin wrote: > Simplify code for update mmsys reg. > > Signed-off-by: Nancy.Lin > Reviewed-by: AngeloGioacchino Del Regno > Reviewed-by: CK Hu > Tested-by: AngeloGioacchino Del Regno > Tested-by: Bo-Chen Chen > Reviewed-by: Nícolas F. R. A. Prado > --- > drivers/soc/mediatek/mtk-mmsys.c | 45 ++++++++++++-------------------- > 1 file changed, 16 insertions(+), 29 deletions(-) > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > index 9a327eb5d9d7..73c8bd27e6ae 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -99,22 +99,27 @@ struct mtk_mmsys { > struct reset_controller_dev rcdev; > }; > > +static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val) > +{ > + u32 tmp; > + > + tmp = readl_relaxed(mmsys->regs + offset); > + tmp = (tmp & ~mask) | (val & mask); I'm not sure about the change in the implementation of mtk_mmsys_update_bits(). Nicolas tried to explain it to me on IRC but I wasn't totally convincing. As we have to go for at least another round of this patches, I'd like to get a clear understanding while it is needed that val bits are set to 1 in the mask. Regards, Matthias > + writel_relaxed(tmp, mmsys->regs + offset); > +} > + > void mtk_mmsys_ddp_connect(struct device *dev, > enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next) > { > struct mtk_mmsys *mmsys = dev_get_drvdata(dev); > const struct mtk_mmsys_routes *routes = mmsys->data->routes; > - u32 reg; > int i; > > for (i = 0; i < mmsys->data->num_routes; i++) > - if (cur == routes[i].from_comp && next == routes[i].to_comp) { > - reg = readl_relaxed(mmsys->regs + routes[i].addr); > - reg &= ~routes[i].mask; > - reg |= routes[i].val; > - writel_relaxed(reg, mmsys->regs + routes[i].addr); > - } > + if (cur == routes[i].from_comp && next == routes[i].to_comp) > + mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, > + routes[i].val); > } > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); > > @@ -124,27 +129,14 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > { > struct mtk_mmsys *mmsys = dev_get_drvdata(dev); > const struct mtk_mmsys_routes *routes = mmsys->data->routes; > - u32 reg; > int i; > > for (i = 0; i < mmsys->data->num_routes; i++) > - if (cur == routes[i].from_comp && next == routes[i].to_comp) { > - reg = readl_relaxed(mmsys->regs + routes[i].addr); > - reg &= ~routes[i].mask; > - writel_relaxed(reg, mmsys->regs + routes[i].addr); > - } > + if (cur == routes[i].from_comp && next == routes[i].to_comp) > + mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, 0); > } > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); > > -static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val) > -{ > - u32 tmp; > - > - tmp = readl_relaxed(mmsys->regs + offset); > - tmp = (tmp & ~mask) | val; > - writel_relaxed(tmp, mmsys->regs + offset); > -} > - > void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val) > { > if (val) > @@ -161,18 +153,13 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l > { > struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev); > unsigned long flags; > - u32 reg; > > spin_lock_irqsave(&mmsys->lock, flags); > > - reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset); > - > if (assert) > - reg &= ~BIT(id); > + mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), 0); > else > - reg |= BIT(id); > - > - writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset); > + mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), BIT(id)); > > spin_unlock_irqrestore(&mmsys->lock, flags); >