From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AA4DC43461 for ; Tue, 15 Sep 2020 05:22:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B93AC2078D for ; Tue, 15 Sep 2020 05:22:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="SRD44rkM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726061AbgIOFWt (ORCPT ); Tue, 15 Sep 2020 01:22:49 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:28155 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726046AbgIOFWs (ORCPT ); Tue, 15 Sep 2020 01:22:48 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1600147367; h=Message-ID: References: In-Reply-To: Subject: Cc: To: From: Date: Content-Transfer-Encoding: Content-Type: MIME-Version: Sender; bh=+DxdXglsCm9GNu2FhjIm9kRGho72XduQ5AptOxX+trE=; b=SRD44rkMj4sIIOLHReKcG/osrNr7oC8tZ92aWS2mVgJTpcj/okRjGYEMaqztiB+mk/DHDWxg eyTdnLGFRcrgYUo+MO65YCY9jPqae8oaxBfMOK9C+HpW2cc0LuvZvoT5vaVi3+ZibgAw1VeI +DsTlnXnEIXctBRnN/Tr83wUkyc= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n04.prod.us-east-1.postgun.com with SMTP id 5f604fa74f13e63f0462764c (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Tue, 15 Sep 2020 05:22:47 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 792F5C433F1; Tue, 15 Sep 2020 05:22:46 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id 60003C433CA; Tue, 15 Sep 2020 05:22:45 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Tue, 15 Sep 2020 10:52:45 +0530 From: Sai Prakash Ranjan To: Stephen Boyd Cc: Andy Gross , Bjorn Andersson , Douglas Anderson , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, "Isaac J. Manjarres" Subject: Re: [PATCHv4 2/2] soc: qcom: llcc: Support chipsets that can write to llcc regs In-Reply-To: <160010921920.4188128.15524650302574745988@swboyd.mtv.corp.google.com> References: <84742b96802d94da00006be8d51cadce4ae04f9f.1599974998.git.saiprakash.ranjan@codeaurora.org> <160010921920.4188128.15524650302574745988@swboyd.mtv.corp.google.com> Message-ID: <590f9bacf06d735a7961ddb8234299ca@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 2020-09-15 00:16, Stephen Boyd wrote: > Quoting Sai Prakash Ranjan (2020-09-14 04:13:00) >> From: "Isaac J. Manjarres" >> >> Older chipsets may not be allowed to configure certain LLCC registers >> as that is handled by the secure side software. However, this is not >> the case for newer chipsets and they must configure these registers >> according to the contents of the SCT table, while keeping in mind that >> older targets may not have these capabilities. So add support to allow >> such configuration of registers to enable capacity based allocation >> and power collapse retention for capable chipsets. >> >> Reason for choosing capacity based allocation rather than the default >> way based allocation is because capacity based allocation allows more >> finer grain partition and provides more flexibility in configuration. >> As for the retention through power collapse, it has an advantage where >> the cache hits are more when we wake up from power collapse although >> it does burn more power but the exact power numbers are not known at >> the moment. >> >> Signed-off-by: Isaac J. Manjarres >> Reviewed-by: Douglas Anderson >> (saiprakash.ranjan@codeaurora.org: use existing config and reword >> commit msg) > > Should be [ not ( > Ok >> Signed-off-by: Sai Prakash Ranjan >> --- >> drivers/soc/qcom/llcc-qcom.c | 27 +++++++++++++++++++++++++-- >> 1 file changed, 25 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/soc/qcom/llcc-qcom.c >> b/drivers/soc/qcom/llcc-qcom.c >> index 60ee31842dea..6aedccff49bb 100644 >> --- a/drivers/soc/qcom/llcc-qcom.c >> +++ b/drivers/soc/qcom/llcc-qcom.c >> @@ -375,6 +382,22 @@ static int qcom_llcc_cfg_program(struct >> platform_device *pdev) >> if (ret) >> return ret; >> >> + if (cfg->need_llcc_cfg) { >> + u32 disable_cap_alloc, retain_pc; >> + >> + disable_cap_alloc = >> llcc_table[i].dis_cap_alloc << llcc_table[i].slice_id; >> + ret = regmap_write(drv_data->bcast_regmap, >> + LLCC_TRP_SCID_DIS_CAP_ALLOC, >> disable_cap_alloc); >> + if (ret) >> + return ret; >> + >> + retain_pc = llcc_table[i].retain_on_pc << >> llcc_table[i].slice_id; >> + ret = regmap_write(drv_data->bcast_regmap, >> + LLCC_TRP_PCB_ACT, retain_pc); >> + if (ret) >> + return ret; >> + } >> + >> if (llcc_table[i].activate_on_init) { >> desc.slice_id = llcc_table[i].slice_id; >> ret = llcc_slice_activate(&desc); > > I thought all of this stuff would move into the config function. So the > for loop is simplified to a function call and return if failure. The config function was specifically for attribute config not for other llcc configs like these, so I will rename qcom_llcc_attr_cfg() to _qcom_llcc_cfg_program() and move everything there. As a side note, I have your mails in my inbox but these messages are not appearing in the list [1]. For Patch 2, its on the list [2]. I have noticed same thing on your messages for previous patches, where your reply for one patch was on the list but the other one was missing, you might have to check that. [1] https://lore.kernel.org/patchwork/patch/1305132/ [2] https://lore.kernel.org/patchwork/patch/1305133/ Same with lore.kernel.org/lkml/ links but since url was big, I gave the above patchwork links. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96F4CC43461 for ; Tue, 15 Sep 2020 05:24:22 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1F4C620738 for ; Tue, 15 Sep 2020 05:24:22 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Manjarres" , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Douglas Anderson , Andy Gross , Bjorn Andersson , linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2020-09-15 00:16, Stephen Boyd wrote: > Quoting Sai Prakash Ranjan (2020-09-14 04:13:00) >> From: "Isaac J. Manjarres" >> >> Older chipsets may not be allowed to configure certain LLCC registers >> as that is handled by the secure side software. However, this is not >> the case for newer chipsets and they must configure these registers >> according to the contents of the SCT table, while keeping in mind that >> older targets may not have these capabilities. So add support to allow >> such configuration of registers to enable capacity based allocation >> and power collapse retention for capable chipsets. >> >> Reason for choosing capacity based allocation rather than the default >> way based allocation is because capacity based allocation allows more >> finer grain partition and provides more flexibility in configuration. >> As for the retention through power collapse, it has an advantage where >> the cache hits are more when we wake up from power collapse although >> it does burn more power but the exact power numbers are not known at >> the moment. >> >> Signed-off-by: Isaac J. Manjarres >> Reviewed-by: Douglas Anderson >> (saiprakash.ranjan@codeaurora.org: use existing config and reword >> commit msg) > > Should be [ not ( > Ok >> Signed-off-by: Sai Prakash Ranjan >> --- >> drivers/soc/qcom/llcc-qcom.c | 27 +++++++++++++++++++++++++-- >> 1 file changed, 25 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/soc/qcom/llcc-qcom.c >> b/drivers/soc/qcom/llcc-qcom.c >> index 60ee31842dea..6aedccff49bb 100644 >> --- a/drivers/soc/qcom/llcc-qcom.c >> +++ b/drivers/soc/qcom/llcc-qcom.c >> @@ -375,6 +382,22 @@ static int qcom_llcc_cfg_program(struct >> platform_device *pdev) >> if (ret) >> return ret; >> >> + if (cfg->need_llcc_cfg) { >> + u32 disable_cap_alloc, retain_pc; >> + >> + disable_cap_alloc = >> llcc_table[i].dis_cap_alloc << llcc_table[i].slice_id; >> + ret = regmap_write(drv_data->bcast_regmap, >> + LLCC_TRP_SCID_DIS_CAP_ALLOC, >> disable_cap_alloc); >> + if (ret) >> + return ret; >> + >> + retain_pc = llcc_table[i].retain_on_pc << >> llcc_table[i].slice_id; >> + ret = regmap_write(drv_data->bcast_regmap, >> + LLCC_TRP_PCB_ACT, retain_pc); >> + if (ret) >> + return ret; >> + } >> + >> if (llcc_table[i].activate_on_init) { >> desc.slice_id = llcc_table[i].slice_id; >> ret = llcc_slice_activate(&desc); > > I thought all of this stuff would move into the config function. So the > for loop is simplified to a function call and return if failure. The config function was specifically for attribute config not for other llcc configs like these, so I will rename qcom_llcc_attr_cfg() to _qcom_llcc_cfg_program() and move everything there. As a side note, I have your mails in my inbox but these messages are not appearing in the list [1]. For Patch 2, its on the list [2]. I have noticed same thing on your messages for previous patches, where your reply for one patch was on the list but the other one was missing, you might have to check that. [1] https://lore.kernel.org/patchwork/patch/1305132/ [2] https://lore.kernel.org/patchwork/patch/1305133/ Same with lore.kernel.org/lkml/ links but since url was big, I gave the above patchwork links. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel