[PATCH] x86/intel_rdt: Fix a typo in Documentation

[PATCH] x86/intel_rdt: Fix a typo in Documentation

[Xiaochen Shen]

The typo is in example 3.

"C0" in "# echo C0 > p0/cpus" is wrong because it specifies core
6-7 instead of wanted core 4-7.

Correct this typo to avoid confusion.

Signed-off-by: Xiaochen Shen <xiaochen.shen@intel.com>
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
---
 Documentation/x86/intel_rdt_ui.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/x86/intel_rdt_ui.txt b/Documentation/x86/intel_rdt_ui.txt
index 0f6d847..c491a1b 100644
--- a/Documentation/x86/intel_rdt_ui.txt
+++ b/Documentation/x86/intel_rdt_ui.txt
@@ -295,7 +295,7 @@ kernel and the tasks running there get 50% of the cache. They should
 also get 50% of memory bandwidth assuming that the cores 4-7 are SMT
 siblings and only the real time threads are scheduled on the cores 4-7.
 
-# echo C0 > p0/cpus
+# echo F0 > p0/cpus
 
 4) Locking between applications
 
-- 
1.8.3.1

Re: [PATCH] x86/intel_rdt: Fix a typo in Documentation

[Thomas Gleixner]

On Wed, 3 May 2017, Xiaochen Shen wrote:

> The typo is in example 3.
> 
> "C0" in "# echo C0 > p0/cpus" is wrong because it specifies core
> 6-7 instead of wanted core 4-7.
> 
> Correct this typo to avoid confusion.
> 
> Signed-off-by: Xiaochen Shen <xiaochen.shen@intel.com>
> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>

That SOB chain is wrong.

Thanks,

	tglx

Re: [PATCH] x86/intel_rdt: Fix a typo in Documentation

[Xiaochen Shen]

Hi Thomas,

I am sorry, this is the reason why I added Fenghua in SOB list:
I have sent this patch to Fenghua for internal review. After that, I sent it
out to LKML.

What is your suggestion to fix? Move Fenghua from "Signed-off-by:" to "Cc:"?
Thank you.

Best regards,
Xiaochen

On 2017/5/9 15:03, Thomas Gleixner wrote:
> On Wed, 3 May 2017, Xiaochen Shen wrote:
> 
>> The typo is in example 3.
>>
>> "C0" in "# echo C0 > p0/cpus" is wrong because it specifies core
>> 6-7 instead of wanted core 4-7.
>>
>> Correct this typo to avoid confusion.
>>
>> Signed-off-by: Xiaochen Shen <xiaochen.shen@intel.com>
>> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
> 
> That SOB chain is wrong.
> 
> Thanks,
> 
> 	tglx
> 

Re: [PATCH] x86/intel_rdt: Fix a typo in Documentation

[Thomas Gleixner]

On Tue, 9 May 2017, Xiaochen Shen wrote:

> Hi Thomas,
> 
> I am sorry, this is the reason why I added Fenghua in SOB list:
> I have sent this patch to Fenghua for internal review. After that, I sent it
> out to LKML.

The SOB chain would have been correct, if Fenghua would have sent your
patch.

> What is your suggestion to fix? Move Fenghua from "Signed-off-by:" to "Cc:"?

Yes, and if Fenghua want's to add his acked/reviewed-by he can do this on
the mailing list.

Thanks,

	tglx

Re: [PATCH] x86/intel_rdt: Fix a typo in Documentation

[Xiaochen Shen]

Thank you, Thomas. I will send out v2 patch with the fix soon.

Best regards,
Xiaochen

On 2017/5/9 15:22, Thomas Gleixner wrote:
> On Tue, 9 May 2017, Xiaochen Shen wrote:
> 
>> Hi Thomas,
>>
>> I am sorry, this is the reason why I added Fenghua in SOB list:
>> I have sent this patch to Fenghua for internal review. After that, I sent it
>> out to LKML.
> 
> The SOB chain would have been correct, if Fenghua would have sent your
> patch.
> 
>> What is your suggestion to fix? Move Fenghua from "Signed-off-by:" to "Cc:"?
> 
> Yes, and if Fenghua want's to add his acked/reviewed-by he can do this on
> the mailing list.
> 
> Thanks,
> 
> 	tglx
> 

[tip:x86/urgent] x86/intel_rdt: Fix a typo in Documentation

[tip-bot for Xiaochen Shen]

Commit-ID:  fb8fb46c56289b3f34b5d90a4ec65e9e4e4544a5
Gitweb:     http://git.kernel.org/tip/fb8fb46c56289b3f34b5d90a4ec65e9e4e4544a5
Author:     Xiaochen Shen <xiaochen.shen@intel.com>
AuthorDate: Wed, 3 May 2017 11:15:56 +0800
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Tue, 9 May 2017 09:41:42 +0200

x86/intel_rdt: Fix a typo in Documentation

Example 3 contains a typo:

"C0" in "# echo C0 > p0/cpus" is wrong because it specifies core
6-7 instead of wanted core 4-7.

Correct this typo to avoid confusion.

Signed-off-by: Xiaochen Shen <xiaochen.shen@intel.com>
Acked-by: Fenghua Yu <fenghua.yu@intel.com>
Cc: vikas.shivappa@linux.intel.com
Cc: tony.luck@intel.com
Link: http://lkml.kernel.org/r/1493781356-24229-1-git-send-email-xiaochen.shen@intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

---
 Documentation/x86/intel_rdt_ui.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/x86/intel_rdt_ui.txt b/Documentation/x86/intel_rdt_ui.txt
index 0f6d847..c491a1b 100644
--- a/Documentation/x86/intel_rdt_ui.txt
+++ b/Documentation/x86/intel_rdt_ui.txt
@@ -295,7 +295,7 @@ kernel and the tasks running there get 50% of the cache. They should
 also get 50% of memory bandwidth assuming that the cores 4-7 are SMT
 siblings and only the real time threads are scheduled on the cores 4-7.
 
-# echo C0 > p0/cpus
+# echo F0 > p0/cpus
 
 4) Locking between applications