From mboxrd@z Thu Jan 1 00:00:00 1970 From: zhoucm1 Subject: Re: [PATCH 1/2] drm/amdgpu: fix re-program vm invalidate eng address range for gfxhub on resume Date: Wed, 17 May 2017 16:19:40 +0800 Message-ID: <591C079C.4070902@amd.com> References: <1495006729-17310-1-git-send-email-ray.huang@amd.com> <591BFF33.2010303@amd.com> <20170517075557.GA31947@hr-amur2> <591C05B5.4090902@amd.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0096630680==" Return-path: In-Reply-To: <591C05B5.4090902-5C7GfCeVMHo@public.gmane.org> List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: Huang Rui Cc: "Deucher, Alexander" , "Huan, Alvin" , "Wang, Ken" , "Koenig, Christian" , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" --===============0096630680== Content-Type: multipart/alternative; boundary="------------010307060204030805040603" --------------010307060204030805040603 Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 8bit see here, I already find dis-advance: enum amd_ip_block_type { AMD_IP_BLOCK_TYPE_COMMON, AMD_IP_BLOCK_TYPE_GMC, AMD_IP_BLOCK_TYPE_IH, AMD_IP_BLOCK_TYPE_SMC, AMD_IP_BLOCK_TYPE_PSP, AMD_IP_BLOCK_TYPE_DCE, AMD_IP_BLOCK_TYPE_GFX, AMD_IP_BLOCK_TYPE_SDMA, AMD_IP_BLOCK_TYPE_UVD, AMD_IP_BLOCK_TYPE_VCE, AMD_IP_BLOCK_TYPE_ACP, AMD_IP_BLOCK_TYPE_GFXHUB, AMD_IP_BLOCK_TYPE_MMHUB }; resume will follow this sequence. but initial sequence is : amdgpu_ip_block_add(adev, &vega10_common_ip_block); amdgpu_ip_block_add(adev, &gfxhub_v1_0_ip_block); amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block); amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block); amdgpu_ip_block_add(adev, &vega10_ih_ip_block); if (amdgpu_fw_load_type == 2 || amdgpu_fw_load_type == -1) amdgpu_ip_block_add(adev, &psp_v3_1_ip_block); if (!amdgpu_sriov_vf(adev)) amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) amdgpu_ip_block_add(adev, &dce_virtual_ip_block); #if defined(CONFIG_DRM_AMD_DC) else if (amdgpu_device_has_dc_support(adev)) amdgpu_ip_block_add(adev, &dm_ip_block); #else # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15." #endif amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block); amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block); amdgpu_ip_block_add(adev, &uvd_v7_0_ip_block); amdgpu_ip_block_add(adev, &vce_v4_0_ip_block); They are different. I remember I asked you if they are same, don't know why you answer 'yes'. With s3 problem still in there, please do this improvement asap. Regards, David Zhou On 2017年05月17日 16:11, zhoucm1 wrote: > > > On 2017年05月17日 15:55, Huang Rui wrote: >> On Wed, May 17, 2017 at 03:43:47PM +0800, Zhou, David(ChunMing) wrote: >>> By this change, I suggest to remove mmhub/gfxhub_v1_0_ip_funcs and >>> their >>> IP block, unify them to gmc ip block, this way we cannot lost setting >>> when resume back. >>> >> From hw side, wo won't have real gmc since this chip, mmhub and >> gfxhub(gc) >> instead of it. Maybe we would better to align with hw desgin. > I don't see any advance, as you said, we still have gmc block in > soc15, why not unify mmhub/gfxhub calls to gmc block? > We can keep mmhub/gfxhub_xxx.c file, but ip_funciton isn't necessary. > > Regards, > David Zhou >> >> Thanks, >> Rui >> >>> Regards, >>> David Zhou >>> >>> On 2017年05月17日 15:38, Huang Rui wrote: >>>> Signed-off-by: Huang Rui >>>> --- >>>> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 +- >>>> 1 file changed, 1 insertion(+), 1 deletion(-) >>>> >>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c >>>> b/drivers/gpu/drm/amd/ >>> amdgpu/gfxhub_v1_0.c >>>> index 005075f..41313514 100644 >>>> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c >>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c >>>> @@ -368,7 +368,7 @@ static int gfxhub_v1_0_suspend(void *handle) >>>> static int gfxhub_v1_0_resume(void *handle) >>>> { >>>> - return 0; >>>> + return gfxhub_v1_0_hw_init(handle); >>>> } >>>> static bool gfxhub_v1_0_is_idle(void *handle) >> _______________________________________________ >> amd-gfx mailing list >> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > > _______________________________________________ > amd-gfx mailing list > amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx --------------010307060204030805040603 Content-Type: text/html; charset="utf-8" Content-Transfer-Encoding: 8bit see here, I already find dis-advance:
enum amd_ip_block_type {
        AMD_IP_BLOCK_TYPE_COMMON,
        AMD_IP_BLOCK_TYPE_GMC,
        AMD_IP_BLOCK_TYPE_IH,
        AMD_IP_BLOCK_TYPE_SMC,
        AMD_IP_BLOCK_TYPE_PSP,           
        AMD_IP_BLOCK_TYPE_DCE,
        AMD_IP_BLOCK_TYPE_GFX,
        AMD_IP_BLOCK_TYPE_SDMA,
        AMD_IP_BLOCK_TYPE_UVD,
        AMD_IP_BLOCK_TYPE_VCE,
        AMD_IP_BLOCK_TYPE_ACP,
        AMD_IP_BLOCK_TYPE_GFXHUB,
        AMD_IP_BLOCK_TYPE_MMHUB
};
resume will follow this sequence.
but initial sequence is :
              amdgpu_ip_block_add(adev, &vega10_common_ip_block);
                amdgpu_ip_block_add(adev, &gfxhub_v1_0_ip_block);
                amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block);
                amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
                amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
                if (amdgpu_fw_load_type == 2 || amdgpu_fw_load_type == -1)
                        amdgpu_ip_block_add(adev, &psp_v3_1_ip_block);
                if (!amdgpu_sriov_vf(adev))
                        amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
                if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
                        amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
                else if (amdgpu_device_has_dc_support(adev))
                        amdgpu_ip_block_add(adev, &dm_ip_block);
#else
#       warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
#endif
                amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block);
                amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block);
                amdgpu_ip_block_add(adev, &uvd_v7_0_ip_block);
                amdgpu_ip_block_add(adev, &vce_v4_0_ip_block);


They are different. I remember I asked you if they are same, don't know why you answer 'yes'.

With s3 problem still in there, please do this improvement asap.

Regards,
David Zhou

On 2017年05月17日 16:11, zhoucm1 wrote:


On 2017年05月17日 15:55, Huang Rui wrote:
On Wed, May 17, 2017 at 03:43:47PM +0800, Zhou, David(ChunMing) wrote:
By this change, I suggest to remove mmhub/gfxhub_v1_0_ip_funcs and their
IP block, unify them to gmc ip block, this way we cannot lost setting
when resume back.

 From hw side, wo won't have real gmc since this chip, mmhub and gfxhub(gc)
instead of it. Maybe we would better to align with hw desgin.
I don't see any advance, as you said, we still have gmc block in soc15, why not unify mmhub/gfxhub calls to gmc block?
We can keep mmhub/gfxhub_xxx.c file, but ip_funciton isn't necessary.

Regards,
David Zhou

Thanks,
Rui

Regards,
David Zhou

On 2017年05月17日 15:38, Huang Rui wrote:
Signed-off-by: Huang Rui <ray.huang-5C7GfCeVMHo@public.gmane.org>
---
   drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 +-
   1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/
amdgpu/gfxhub_v1_0.c
index 005075f..41313514 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -368,7 +368,7 @@ static int gfxhub_v1_0_suspend(void *handle)
     static int gfxhub_v1_0_resume(void *handle)
   {
-     return 0;
+     return gfxhub_v1_0_hw_init(handle);
   }
     static bool gfxhub_v1_0_is_idle(void *handle)
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