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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id b16si2209033qkj.311.2017.05.17.07.06.54 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 17 May 2017 07:06:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Received: from localhost ([::1]:49154 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dAzbK-000627-4f for alex.bennee@linaro.org; Wed, 17 May 2017 10:06:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36688) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dAzWT-000451-Ng for qemu-arm@nongnu.org; Wed, 17 May 2017 10:01:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dAzWO-0002ZQ-PR for qemu-arm@nongnu.org; Wed, 17 May 2017 10:01:53 -0400 Received: from bran.ispras.ru ([83.149.199.196]:46564 helo=smtp.ispras.ru) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dAzWO-0002X1-H7 for qemu-arm@nongnu.org; Wed, 17 May 2017 10:01:48 -0400 Received: from [10.10.2.131] (castle.intra.ispras.ru [10.10.2.131]) by smtp.ispras.ru (Postfix) with ESMTP id 6845960E77 for ; Wed, 17 May 2017 17:01:45 +0300 (MSK) Message-ID: <591C57C9.6070202@ispras.ru> Date: Wed, 17 May 2017 17:01:45 +0300 From: Sergey Smolov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:14.0) Gecko/20120713 Thunderbird/14.0 MIME-Version: 1.0 To: qemu-arm@nongnu.org Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 83.149.199.196 X-Mailman-Approved-At: Wed, 17 May 2017 10:06:44 -0400 Subject: [Qemu-arm] [aarch64] how to get the value is stored by MSR insn X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: SJAaR1oBOAkb Hello, List! I'm running an Aarch64 assembler program on QEMU. The program starts from the following instructions: movz x0, #0x50, LSL #0 msr vbar_el1, x0 My task is to print the value is stored into the vbar_el1 register to the console (it should be equal to 0x50, I think). Here is what I have in target/arm/translate-a64.c that is related to MSR instruction simulation: [code] /* C5.6.129 MRS - move from system register * C5.6.131 MSR (register) - move to system register * C5.6.204 SYS * C5.6.205 SYSL * These are all essentially the same insn in 'read' and 'write' * versions, with varying op0 fields. */ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, unsigned int op0, unsigned int op1, unsigned int op2, unsigned int crn, unsigned int crm, unsigned int rt) { .... if (isread) { ... } else { if (ri->type & ARM_CP_CONST) { /* If not forbidden by access permissions, treat as WI */ return; } else if (ri->writefn) { qemu_log("is-writefn\n"); TCGv_ptr tmpptr; tmpptr = tcg_const_ptr(ri); gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt); tcg_temp_free_ptr(tmpptr); } else { tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset); } } [code] In my case the branch "else if (ri->writefn)" is executed. I've tried to take the value that is stored to vbar_el1 from tcg_rt variable with the help of GET_TCGV_I64 macro, but it returns the value (0x19) that is different from the right one (0x50). In what direction should I dig? -- Sincerely yours, Sergey Smolov