Re: [PATCH 6/7] drm/amdgpu: stop joining VM PTE updates

["Zhang, Jerry (Junwei)" <Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>]

On 05/17/2017 06:08 PM, Zhou, David(ChunMing) wrote:
>
> Patch#2: Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
> Patch#3: RB should be from Hawking, so Acked-by: Chunming Zhou <david1.zhou@amd.com>
> Patch#5 #6, are Reviewed-by: Chunming Zhou <david1.zhou@amd.com>

Feel free to add my RB about Patch #2 ~ #5

Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>

Jerry

>
> For patch#7, further transfer +1 page table, I need a bit time of tomorrow.
>
> Regards,
> David Zhou
>
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Christian K?nig
> Sent: Wednesday, May 17, 2017 5:23 PM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH 6/7] drm/amdgpu: stop joining VM PTE updates
>
> From: Christian König <christian.koenig@amd.com>
>
> This isn't beneficial any more since VRAM allocations are now split so that they fits into a single page table.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 61 ++++------------------------------
>   1 file changed, 7 insertions(+), 54 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 6a926f4..860a669 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -1191,41 +1191,12 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
>   	struct amdgpu_device *adev = params->adev;
>   	const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1;
>
> -	uint64_t cur_pe_start, cur_nptes, cur_dst;
> -	uint64_t addr; /* next GPU address to be updated */
> +	uint64_t addr, pe_start;
>   	struct amdgpu_bo *pt;
> -	unsigned nptes; /* next number of ptes to be updated */
> -	uint64_t next_pe_start;
> -
> -	/* initialize the variables */
> -	addr = start;
> -	pt = amdgpu_vm_get_pt(params, addr);
> -	if (!pt) {
> -		pr_err("PT not found, aborting update_ptes\n");
> -		return -EINVAL;
> -	}
> -
> -	if (params->shadow) {
> -		if (!pt->shadow)
> -			return 0;
> -		pt = pt->shadow;
> -	}
> -	if ((addr & ~mask) == (end & ~mask))
> -		nptes = end - addr;
> -	else
> -		nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask);
> -
> -	cur_pe_start = amdgpu_bo_gpu_offset(pt);
> -	cur_pe_start += (addr & mask) * 8;
> -	cur_nptes = nptes;
> -	cur_dst = dst;
> -
> -	/* for next ptb*/
> -	addr += nptes;
> -	dst += nptes * AMDGPU_GPU_PAGE_SIZE;
> +	unsigned nptes;
>
>   	/* walk over the address space and update the page tables */
> -	while (addr < end) {
> +	for (addr = start; addr < end; addr += nptes) {
>   		pt = amdgpu_vm_get_pt(params, addr);
>   		if (!pt) {
>   			pr_err("PT not found, aborting update_ptes\n"); @@ -1243,33 +1214,15 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
>   		else
>   			nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask);
>
> -		next_pe_start = amdgpu_bo_gpu_offset(pt);
> -		next_pe_start += (addr & mask) * 8;
> -
> -		if ((cur_pe_start + 8 * cur_nptes) == next_pe_start &&
> -		    ((cur_nptes + nptes) <= AMDGPU_VM_MAX_UPDATE_SIZE)) {
> -			/* The next ptb is consecutive to current ptb.
> -			 * Don't call the update function now.
> -			 * Will update two ptbs together in future.
> -			*/
> -			cur_nptes += nptes;
> -		} else {
> -			params->func(params, cur_pe_start, cur_dst, cur_nptes,
> -				     AMDGPU_GPU_PAGE_SIZE, flags);
> +		pe_start = amdgpu_bo_gpu_offset(pt);
> +		pe_start += (addr & mask) * 8;
>
> -			cur_pe_start = next_pe_start;
> -			cur_nptes = nptes;
> -			cur_dst = dst;
> -		}
> +		params->func(params, pe_start, dst, nptes,
> +			     AMDGPU_GPU_PAGE_SIZE, flags);
>
> -		/* for next ptb*/
> -		addr += nptes;
>   		dst += nptes * AMDGPU_GPU_PAGE_SIZE;
>   	}
>
> -	params->func(params, cur_pe_start, cur_dst, cur_nptes,
> -		     AMDGPU_GPU_PAGE_SIZE, flags);
> -
>   	return 0;
>   }
>
> --
> 2.7.4
>
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