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[187.189.51.143]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5f2db579309sm770528eaf.16.2024.12.12.06.49.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Dec 2024 06:49:12 -0800 (PST) Message-ID: <592f8ef2-048f-4f2c-a7d1-704371530a0b@linaro.org> Date: Thu, 12 Dec 2024 08:49:09 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] hw/display: refine upper limit for offset value in assert check To: gerben@altlinux.org, fred.konrad@greensocs.com, qemu-devel@nongnu.org Cc: sdl.qemu@linuxtesting.org, David Meliksetyan References: <20241212114554.517379-1-gerben@altlinux.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <20241212114554.517379-1-gerben@altlinux.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c30; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 12/12/24 05:45, gerben@altlinux.org wrote: > From: Denis Rastyogin > > Accessing an element of the s->core_registers array > with a size of 236 (0x3AC) may lead to a buffer overflow, > as the index 'offset' can exceed the valid range and reach values > up to 5139 (0x504C >> 2). This change addresses > a potential vulnerability when writing data. > > Found by Linux Verification Center (linuxtesting.org) with SVACE. > > Reported-by: David Meliksetyan > Signed-off-by: Denis Rastyogin > --- > hw/display/xlnx_dp.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c > index 6ab2335499..69ccc7ccc2 100644 > --- a/hw/display/xlnx_dp.c > +++ b/hw/display/xlnx_dp.c > @@ -743,6 +743,7 @@ static void xlnx_dp_write(void *opaque, hwaddr offset, uint64_t value, > DPRINTF("core write @%" PRIx64 " = 0x%8.8" PRIX64 "\n", offset, value); > > offset = offset >> 2; > + assert(offset <= (0x3AC >> 2)); > > switch (offset) { > /* > @@ -896,7 +897,6 @@ static void xlnx_dp_write(void *opaque, hwaddr offset, uint64_t value, > xlnx_dp_update_irq(s); > break; > default: > - assert(offset <= (0x504C >> 2)); > s->core_registers[offset] = value; > break; > } Why are you moving the assert? The switch statement takes care of sorting non-default values of offset. More correct would be to use DP_CORE_REG_ARRAY_SIZE in the assert, along with a comment that the io region has been sized exactly to fit core_registers[]. r~