From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mark yao Subject: Re: [PATCH] drm: bridge: synopsys/dw-hdmi: Provide default configuration function for HDMI 2.0 PHY Date: Thu, 22 Jun 2017 16:25:07 +0800 Message-ID: <594B7EE3.9050202@rock-chips.com> References: <6071fd12-2cda-cd1f-2607-9a498f588040@synopsys.com> <3690108.zYIGBGnVBz@avalon> <1941ce39-1a8e-5e16-bdc2-71d988ee00d6@synopsys.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.139]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5DF126E5FE for ; Thu, 22 Jun 2017 08:25:17 +0000 (UTC) In-Reply-To: <1941ce39-1a8e-5e16-bdc2-71d988ee00d6@synopsys.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Jose Abreu , Laurent Pinchart Cc: Laurent Pinchart , linux-kernel@vger.kernel.org, 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X-ABS-CHECKED: 4 X-RL-SENDER: mark.yao@rock-chips.com X-FST-TO: yang.zheng@rock-chips.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: mark.yao@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH] drm: bridge: synopsys/dw-hdmi: Provide default configuration function for HDMI 2.0 PHY To: Jose Abreu , Laurent Pinchart References: <6071fd12-2cda-cd1f-2607-9a498f588040@synopsys.com> <3690108.zYIGBGnVBz@avalon> <1941ce39-1a8e-5e16-bdc2-71d988ee00d6@synopsys.com> Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Kieran Bingham , Laurent Pinchart , Archit Taneja , Andrzej Hajda , Carlos Palminha , =?UTF-8?B?6YOR6Ziz?= From: Mark yao Message-ID: <594B7EE3.9050202@rock-chips.com> Date: Thu, 22 Jun 2017 16:25:07 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <1941ce39-1a8e-5e16-bdc2-71d988ee00d6@synopsys.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jose Sorry miss your email and Sorry for the late reply I can sure that your patch works on our rk3399 platform. my internal kernel already has similar patch, using hdmi_phy_configure_dwc_hdmi_3d_tx() for hdmi 2.0 phy, good works with many video modes (4k, 1080p, 720p etc.), I'm not familiar with hdmi, but hdmi display actually works for us. And, I had tried the 4.12-rc1 kernel with your patch, display works good. So: Tested-by: Mark Yao On 2017年06月13日 22:11, Jose Abreu wrote: > Hi Laurent, > > > Sorry for the late reply! > > > On 10-06-2017 09:50, Laurent Pinchart wrote: >> Hi Jose, >> >> On Friday 09 Jun 2017 13:53:12 Jose Abreu wrote: >>> On 09-06-2017 12:04, Jose Abreu wrote: >>>> Currently HDMI 2.0 PHYs do not have a default configuration function. >>>> >>>> As these PHYs have the same register layout as the 3D PHYs we can >>>> safely use the default configuration function. >>> I may have been a little to fast arriving at this conclusion. I >>> mean most of the registers match but in the configuration >>> function there are registers that do not match. Did you actually >>> test this configuration function with an HDMI 2.0 phy? And did >>> you test with different video modes? From my experience the phy >>> may be wrongly configured and sometimes work anyway. >>> >>> Do please retest with as many video modes as you can and give me >>> your phy ID (read from controller config reg HDMI_CONFIG2_ID). >> The Renesas R-Car Gen3 HDMI PHY reports an DWC HDMI 2.0 TX PHY ID, but has a >> configuration function (rcar_hdmi_phy_configure() in drivers/gpu/drm/rcar- >> du/rcar_dw_hdmi.c) that doesn't match hdmi_phy_configure_dwc_hdmi_3d_tx(). >> From the information I have been given the layout of the configuration >> registers haven't been changed by Renesas. I know we've briefly discussed this >> in the past, but I'd appreciate if you could have a second look and tell me >> what you think. > Yup, yours seems correct. Though at the time you submitted I > found it odd that only 3 registers needed to be written whilst > for HDMI 2.0 phys I have here 6 registers, but you said it is > working so I though your phy was different ... > > Even so, one thing I would like to know is what was the max > resolution you tested? I see you have clock values up to 297MHz, > so 4k@30Hz? If I send a patch with a general config function for > HDMI 2.0 phys can you test it on your platform? > > Best regards, > Jose Miguel Abreu > >>>> If, for some reason, >>>> >>>> the PHY is custom this change will not make any impact because >>>> in configuration function we prefer the pdata provided configuration >>>> function over the internal one. >>>> >>>> This patch is based on today's drm-misc-next branch. >>>> >>>> Signed-off-by: Jose Abreu >>>> Cc: Kieran Bingham >>>> Cc: Laurent Pinchart >>>> Cc: Archit Taneja >>>> Cc: Andrzej Hajda >>>> Cc: Mark Yao >>>> Cc: Carlos Palminha >>>> --- >>>> >>>> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 1 + >>>> 1 file changed, 1 insertion(+) >>>> >>>> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c >>>> b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index ead1124..10c8d8c 100644 >>>> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c >>>> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c >>>> @@ -2170,6 +2170,7 @@ static irqreturn_t dw_hdmi_irq(int irq, void >>>> *dev_id) >>>> .name = "DWC HDMI 2.0 TX PHY", >>>> .gen = 2, >>>> .has_svsret = true, >>>> + .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, >>>> }, { >>>> .type = DW_HDMI_PHY_VENDOR_PHY, >>>> .name = "Vendor PHY", > > > -- Ｍark Yao