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diff for duplicates of <5976FA39.6070803@baylibre.com>

diff --git a/a/1.txt b/N1/1.txt
index 358a4cc..a44c632 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,6 +1,6 @@
 
 
-Le 22/07/2017 20:58, Martin Blumenstingl a ?crit :
+Le 22/07/2017 20:58, Martin Blumenstingl a écrit :
 > The clock controller provides a few reset lines as well. Add the
 > #reset-cells property so we can pass the CPU soft reset lines to their
 > corresponding CPU cores.
@@ -17,7 +17,7 @@ Le 22/07/2017 20:58, Martin Blumenstingl a ?crit :
 > +++ b/arch/arm/boot/dts/meson8.dtsi
 > @@ -168,6 +168,7 @@
 >  &cbus {
->  	clkc: clock-controller at 4000 {
+>  	clkc: clock-controller@4000 {
 >  		#clock-cells = <1>;
 > +		#reset-cells = <1>;
 >  		compatible = "amlogic,meson8-clkc";
@@ -29,7 +29,7 @@ Le 22/07/2017 20:58, Martin Blumenstingl a ?crit :
 > +++ b/arch/arm/boot/dts/meson8b.dtsi
 > @@ -119,6 +119,7 @@
 >  &cbus {
->  	clkc: clock-controller at 4000 {
+>  	clkc: clock-controller@4000 {
 >  		#clock-cells = <1>;
 > +		#reset-cells = <1>;
 >  		compatible = "amlogic,meson8b-clkc";
diff --git a/a/content_digest b/N1/content_digest
index 9b177f3..e555ac1 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,14 +1,25 @@
  "ref\020170722185807.10504-1-martin.blumenstingl@googlemail.com\0"
  "ref\020170722185807.10504-4-martin.blumenstingl@googlemail.com\0"
- "From\0narmstrong@baylibre.com (Neil Armstrong)\0"
- "Subject\0[PATCH v2 3/3] ARM: dts: meson: mark the clock controller also as reset controller\0"
+ "From\0Neil Armstrong <narmstrong@baylibre.com>\0"
+ "Subject\0Re: [PATCH v2 3/3] ARM: dts: meson: mark the clock controller also as reset controller\0"
  "Date\0Tue, 25 Jul 2017 09:58:49 +0200\0"
- "To\0linus-amlogic@lists.infradead.org\0"
+ "To\0Martin Blumenstingl <martin.blumenstingl@googlemail.com>"
+  linux-amlogic@lists.infradead.org
+  khilman@baylibre.com
+  carlo@caione.org
+  jbrunet@baylibre.com
+  linux-clk@vger.kernel.org
+ " robh+dt@kernel.org\0"
+ "Cc\0devicetree@vger.kernel.org"
+  linux@armlinux.org.uk
+  mark.rutland@arm.com
+  mturquette@baylibre.com
+ " sboyd@codeaurora.org\0"
  "\00:1\0"
  "b\0"
  "\n"
  "\n"
- "Le 22/07/2017 20:58, Martin Blumenstingl a ?crit :\n"
+ "Le 22/07/2017 20:58, Martin Blumenstingl a \303\251crit :\n"
  "> The clock controller provides a few reset lines as well. Add the\n"
  "> #reset-cells property so we can pass the CPU soft reset lines to their\n"
  "> corresponding CPU cores.\n"
@@ -25,7 +36,7 @@
  "> +++ b/arch/arm/boot/dts/meson8.dtsi\n"
  "> @@ -168,6 +168,7 @@\n"
  ">  &cbus {\n"
- ">  \tclkc: clock-controller at 4000 {\n"
+ ">  \tclkc: clock-controller@4000 {\n"
  ">  \t\t#clock-cells = <1>;\n"
  "> +\t\t#reset-cells = <1>;\n"
  ">  \t\tcompatible = \"amlogic,meson8-clkc\";\n"
@@ -37,7 +48,7 @@
  "> +++ b/arch/arm/boot/dts/meson8b.dtsi\n"
  "> @@ -119,6 +119,7 @@\n"
  ">  &cbus {\n"
- ">  \tclkc: clock-controller at 4000 {\n"
+ ">  \tclkc: clock-controller@4000 {\n"
  ">  \t\t#clock-cells = <1>;\n"
  "> +\t\t#reset-cells = <1>;\n"
  ">  \t\tcompatible = \"amlogic,meson8b-clkc\";\n"
@@ -47,4 +58,4 @@
  "\n"
  Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
 
-c3adfc8a642c37e3fd0435ad773d4d7c8e73c41513b1b7b559df8d38a6fab3c2
+39906db294920e66bb7fc997f86f62243d7f3c880417c90c4833d86990e39227

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