diff for duplicates of <5976FAAF.9070309@baylibre.com> diff --git a/a/content_digest b/N1/content_digest index a3b5f21..e8c479d 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -3,7 +3,7 @@ "From\0narmstrong@baylibre.com (Neil Armstrong)\0" "Subject\0[PATCH v4 6/7] ARM: dts: meson8: add support for booting the secondary CPU cores\0" "Date\0Tue, 25 Jul 2017 10:00:47 +0200\0" - "To\0linus-amlogic@lists.infradead.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "\n" @@ -98,4 +98,4 @@ "\n" Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> -1f5654ea2610c6b648577cd030433713797d793082ffad5410ff1eef4ba917ef +28edb2518454c5492deafb824681bde670991a98d92a509c4a08c3ed4fd2a370
diff --git a/a/1.txt b/N2/1.txt index 0937c73..715f830 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,6 +1,6 @@ -Le 22/07/2017 21:19, Martin Blumenstingl a ?crit : +Le 22/07/2017 21:19, Martin Blumenstingl a écrit : > Booting the secondary CPU cores involves the following nodes/devices: > - SCU (Snoop-Control-Unit, for which we already have a DT node) > - a reset line for each CPU core, provided by the reset-controller @@ -14,8 +14,8 @@ Le 22/07/2017 21:19, Martin Blumenstingl a ?crit : > This adds all required nodes and properties to boot the secondary CPU > cores. > -> Suggested-by: Carlo Caione <carlo@caione.org> -> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> +> Suggested-by: Carlo Caione <carlo-KA+7E9HrN00dnm+yROfE0A@public.gmane.org> +> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org> > --- > arch/arm/boot/dts/meson8.dtsi | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) @@ -32,7 +32,7 @@ Le 22/07/2017 21:19, Martin Blumenstingl a ?crit : > + resets = <&clkc RESETID_CPU0_SOFT_RESET>; > }; > -> cpu at 201 { +> cpu@201 { > @@ -67,6 +69,8 @@ > compatible = "arm,cortex-a9"; > next-level-cache = <&L2>; @@ -41,7 +41,7 @@ Le 22/07/2017 21:19, Martin Blumenstingl a ?crit : > + resets = <&clkc RESETID_CPU1_SOFT_RESET>; > }; > -> cpu at 202 { +> cpu@202 { > @@ -74,6 +78,8 @@ > compatible = "arm,cortex-a9"; > next-level-cache = <&L2>; @@ -50,7 +50,7 @@ Le 22/07/2017 21:19, Martin Blumenstingl a ?crit : > + resets = <&clkc RESETID_CPU2_SOFT_RESET>; > }; > -> cpu at 203 { +> cpu@203 { > @@ -81,6 +87,8 @@ > compatible = "arm,cortex-a9"; > next-level-cache = <&L2>; @@ -64,12 +64,12 @@ Le 22/07/2017 21:19, Martin Blumenstingl a ?crit : > }; /* end of / */ > > &aobus { -> + pmu: pmu at e0 { +> + pmu: pmu@e0 { > + compatible = "amlogic,meson8-pmu", "syscon"; > + reg = <0xe0 0x8>; > + }; > + -> pinctrl_aobus: pinctrl at 84 { +> pinctrl_aobus: pinctrl@84 { > compatible = "amlogic,meson8-aobus-pinctrl"; > reg = <0x84 0xc>; > @@ -249,6 +262,13 @@ @@ -77,7 +77,7 @@ Le 22/07/2017 21:19, Martin Blumenstingl a ?crit : > }; > > +&ahb_sram { -> + smp-sram at 1ff80 { +> + smp-sram@1ff80 { > + compatible = "amlogic,meson8-smp-sram"; > + reg = <0x1ff80 0x8>; > + }; @@ -88,4 +88,8 @@ Le 22/07/2017 21:19, Martin Blumenstingl a ?crit : > clock-names = "stmmaceth"; > -Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> +Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N2/content_digest index a3b5f21..b4fbb95 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,14 +1,24 @@ "ref\020170722191946.22938-1-martin.blumenstingl@googlemail.com\0" "ref\020170722191946.22938-7-martin.blumenstingl@googlemail.com\0" - "From\0narmstrong@baylibre.com (Neil Armstrong)\0" - "Subject\0[PATCH v4 6/7] ARM: dts: meson8: add support for booting the secondary CPU cores\0" + "ref\020170722191946.22938-7-martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org\0" + "From\0Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>\0" + "Subject\0Re: [PATCH v4 6/7] ARM: dts: meson8: add support for booting the secondary CPU cores\0" "Date\0Tue, 25 Jul 2017 10:00:47 +0200\0" - "To\0linus-amlogic@lists.infradead.org\0" + "To\0Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>" + linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org + carlo-KA+7E9HrN00dnm+yROfE0A@public.gmane.org + " linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org\0" + "Cc\0mark.rutland-5wv7dgnIgG8@public.gmane.org" + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org + " arnd-r2nGTMty4D4@public.gmane.org\0" "\00:1\0" "b\0" "\n" "\n" - "Le 22/07/2017 21:19, Martin Blumenstingl a ?crit :\n" + "Le 22/07/2017 21:19, Martin Blumenstingl a \303\251crit :\n" "> Booting the secondary CPU cores involves the following nodes/devices:\n" "> - SCU (Snoop-Control-Unit, for which we already have a DT node)\n" "> - a reset line for each CPU core, provided by the reset-controller\n" @@ -22,8 +32,8 @@ "> This adds all required nodes and properties to boot the secondary CPU\n" "> cores.\n" "> \n" - "> Suggested-by: Carlo Caione <carlo@caione.org>\n" - "> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n" + "> Suggested-by: Carlo Caione <carlo-KA+7E9HrN00dnm+yROfE0A@public.gmane.org>\n" + "> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>\n" "> ---\n" "> arch/arm/boot/dts/meson8.dtsi | 20 ++++++++++++++++++++\n" "> 1 file changed, 20 insertions(+)\n" @@ -40,7 +50,7 @@ "> +\t\t\tresets = <&clkc RESETID_CPU0_SOFT_RESET>;\n" "> \t\t};\n" "> \n" - "> \t\tcpu at 201 {\n" + "> \t\tcpu@201 {\n" "> @@ -67,6 +69,8 @@\n" "> \t\t\tcompatible = \"arm,cortex-a9\";\n" "> \t\t\tnext-level-cache = <&L2>;\n" @@ -49,7 +59,7 @@ "> +\t\t\tresets = <&clkc RESETID_CPU1_SOFT_RESET>;\n" "> \t\t};\n" "> \n" - "> \t\tcpu at 202 {\n" + "> \t\tcpu@202 {\n" "> @@ -74,6 +78,8 @@\n" "> \t\t\tcompatible = \"arm,cortex-a9\";\n" "> \t\t\tnext-level-cache = <&L2>;\n" @@ -58,7 +68,7 @@ "> +\t\t\tresets = <&clkc RESETID_CPU2_SOFT_RESET>;\n" "> \t\t};\n" "> \n" - "> \t\tcpu at 203 {\n" + "> \t\tcpu@203 {\n" "> @@ -81,6 +87,8 @@\n" "> \t\t\tcompatible = \"arm,cortex-a9\";\n" "> \t\t\tnext-level-cache = <&L2>;\n" @@ -72,12 +82,12 @@ "> }; /* end of / */\n" "> \n" "> &aobus {\n" - "> +\tpmu: pmu at e0 {\n" + "> +\tpmu: pmu@e0 {\n" "> +\t\tcompatible = \"amlogic,meson8-pmu\", \"syscon\";\n" "> +\t\treg = <0xe0 0x8>;\n" "> +\t};\n" "> +\n" - "> \tpinctrl_aobus: pinctrl at 84 {\n" + "> \tpinctrl_aobus: pinctrl@84 {\n" "> \t\tcompatible = \"amlogic,meson8-aobus-pinctrl\";\n" "> \t\treg = <0x84 0xc>;\n" "> @@ -249,6 +262,13 @@\n" @@ -85,7 +95,7 @@ "> };\n" "> \n" "> +&ahb_sram {\n" - "> +\tsmp-sram at 1ff80 {\n" + "> +\tsmp-sram@1ff80 {\n" "> +\t\tcompatible = \"amlogic,meson8-smp-sram\";\n" "> +\t\treg = <0x1ff80 0x8>;\n" "> +\t};\n" @@ -96,6 +106,10 @@ "> \tclock-names = \"stmmaceth\";\n" "> \n" "\n" - Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> + "Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -1f5654ea2610c6b648577cd030433713797d793082ffad5410ff1eef4ba917ef +f0bd228e8bdd1414c6c823c99f70b42911830b26645aec12dc0ecf65c6ff4478
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