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From: "Peter Wang (王信友)" <peter.wang@mediatek.com>
To: "linux-scsi@vger.kernel.org" <linux-scsi@vger.kernel.org>,
	"bvanassche@acm.org" <bvanassche@acm.org>,
	"martin.petersen@oracle.com" <martin.petersen@oracle.com>
Cc: "quic_asutoshd@guicinc.com" <quic_asutoshd@guicinc.com>
Subject: Re: [PATCH v1] ufs: core: decouple CQE processing from spinlock critical section
Date: Sat, 16 May 2026 11:52:56 +0000	[thread overview]
Message-ID: <599a2ea183cce202170ff3c06d71f42d32a01198.camel@mediatek.com> (raw)
In-Reply-To: <2ed721de-0410-413a-bda1-99b5313b072d@acm.org>

On Fri, 2026-05-15 at 09:43 -0700, Bart Van Assche wrote:
> (6) The host controller completes the corresponding commands and
> stores
>      the CQEs in CQ slots 8, 0, 1 and 2. Hence, slots 0, 1 and 2 are
>      overwritten although the overwritten CQEs have not yet been
>      processed.

Sorry, I might have misunderstood your point. 
Are you saying that the HWQ depth is only 9?

Thanks
Peter

      parent reply	other threads:[~2026-05-16 11:53 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-14  8:26 [PATCH v1] ufs: core: decouple CQE processing from spinlock critical section peter.wang
2026-05-14 16:22 ` Bart Van Assche
2026-05-15  8:13   ` Peter Wang (王信友)
2026-05-15 16:43     ` Bart Van Assche
2026-05-16  6:24       ` Peter Wang (王信友)
2026-05-16 14:01         ` Bart Van Assche
2026-05-16 11:52       ` Peter Wang (王信友) [this message]

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