From: Frank Rowand <frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
"Robert P. J. Day"
<rpjday-L09J2beyid0N/H6P543EQg@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: more pedantic proofing of DTSpec version 0.1
Date: Tue, 5 Sep 2017 14:14:03 -0700 [thread overview]
Message-ID: <59AF139B.5090501@gmail.com> (raw)
In-Reply-To: <20170831205659.67fvxjdgggbifuy6@rob-hp-laptop>
On 08/31/17 13:56, Rob Herring wrote:
> On Sat, Aug 26, 2017 at 10:50:46AM -0400, Robert P. J. Day wrote:
>>
< snip >
>> p. 25: table 3.6, the acronym "PIR" comes out of nowhere, perhaps
>> explain it the first time?
>
> I'm drawing a blank as to what that is.
According to the Mindshare book: PowerPC System Architecture:
"Processor ID Register (PIR)
The PIR is a 32-bit register that can be used by the OS to assign
an ID to the processor. Aside from any OS-specific usage of the
assigned ID, the processor uses the ID when communicating with
I/O devices."
< snip >
--
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next prev parent reply other threads:[~2017-09-05 21:14 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-26 14:50 more pedantic proofing of DTSpec version 0.1 Robert P. J. Day
[not found] ` <alpine.LFD.2.20.1708210705090.28188-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
2017-08-31 20:56 ` Rob Herring
2017-08-31 21:09 ` Robert P. J. Day
2017-09-05 21:14 ` Frank Rowand [this message]
[not found] ` <59AF139B.5090501-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-09-05 21:20 ` Robert P. J. Day
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