diff for duplicates of <5A3CD286.2010705@hisilicon.com> diff --git a/a/1.txt b/N1/1.txt index a74fb82..7065489 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -72,7 +72,7 @@ Wei > + capacity-dmips-mhz = <592>; > }; > -> cpu1: cpu at 1 { +> cpu1: cpu@1 { > @@ -70,6 +71,7 @@ > enable-method = "psci"; > next-level-cache = <&A53_L2>; @@ -80,7 +80,7 @@ Wei > + capacity-dmips-mhz = <592>; > }; > -> cpu2: cpu at 2 { +> cpu2: cpu@2 { > @@ -79,6 +81,7 @@ > enable-method = "psci"; > next-level-cache = <&A53_L2>; @@ -88,7 +88,7 @@ Wei > + capacity-dmips-mhz = <592>; > }; > -> cpu3: cpu at 3 { +> cpu3: cpu@3 { > @@ -88,6 +91,7 @@ > enable-method = "psci"; > next-level-cache = <&A53_L2>; @@ -96,7 +96,7 @@ Wei > + capacity-dmips-mhz = <592>; > }; > -> cpu4: cpu at 100 { +> cpu4: cpu@100 { > @@ -101,6 +105,7 @@ > &CPU_SLEEP > &CLUSTER_SLEEP_1 @@ -104,7 +104,7 @@ Wei > + capacity-dmips-mhz = <1024>; > }; > -> cpu5: cpu at 101 { +> cpu5: cpu@101 { > @@ -114,6 +119,7 @@ > &CPU_SLEEP > &CLUSTER_SLEEP_1 @@ -112,7 +112,7 @@ Wei > + capacity-dmips-mhz = <1024>; > }; > -> cpu6: cpu at 102 { +> cpu6: cpu@102 { > @@ -127,6 +133,7 @@ > &CPU_SLEEP > &CLUSTER_SLEEP_1 @@ -120,7 +120,7 @@ Wei > + capacity-dmips-mhz = <1024>; > }; > -> cpu7: cpu at 103 { +> cpu7: cpu@103 { > @@ -140,6 +147,7 @@ > &CPU_SLEEP > &CLUSTER_SLEEP_1 diff --git a/a/content_digest b/N1/content_digest index 3242389..671a1c9 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,8 +1,16 @@ "ref\01513174866-6678-1-git-send-email-valentin.schneider@arm.com\0" - "From\0xuwei5@hisilicon.com (Wei Xu)\0" - "Subject\0[PATCH] arm64: dts: hisilicon: Add hi3660 cpu capacity-dmips-mhz information\0" + "From\0Wei Xu <xuwei5@hisilicon.com>\0" + "Subject\0Re: [PATCH] arm64: dts: hisilicon: Add hi3660 cpu capacity-dmips-mhz information\0" "Date\0Fri, 22 Dec 2017 09:38:14 +0000\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Valentin Schneider <valentin.schneider@arm.com>" + " linux-kernel@vger.kernel.org\0" + "Cc\0Rob Herring <robh+dt@kernel.org>" + Mark Rutland <mark.rutland@arm.com> + Catalin Marinas <catalin.marinas@arm.com> + Will Deacon <will.deacon@arm.com> + Dietmar Eggemann <dietmar.eggemann@arm.com> + linux-arm-kernel@lists.infradead.org + " devicetree@vger.kernel.org\0" "\00:1\0" "b\0" "Hi Valentin,\n" @@ -79,7 +87,7 @@ "> +\t\t\tcapacity-dmips-mhz = <592>;\n" "> \t\t};\n" "> \n" - "> \t\tcpu1: cpu at 1 {\n" + "> \t\tcpu1: cpu@1 {\n" "> @@ -70,6 +71,7 @@\n" "> \t\t\tenable-method = \"psci\";\n" "> \t\t\tnext-level-cache = <&A53_L2>;\n" @@ -87,7 +95,7 @@ "> +\t\t\tcapacity-dmips-mhz = <592>;\n" "> \t\t};\n" "> \n" - "> \t\tcpu2: cpu at 2 {\n" + "> \t\tcpu2: cpu@2 {\n" "> @@ -79,6 +81,7 @@\n" "> \t\t\tenable-method = \"psci\";\n" "> \t\t\tnext-level-cache = <&A53_L2>;\n" @@ -95,7 +103,7 @@ "> +\t\t\tcapacity-dmips-mhz = <592>;\n" "> \t\t};\n" "> \n" - "> \t\tcpu3: cpu at 3 {\n" + "> \t\tcpu3: cpu@3 {\n" "> @@ -88,6 +91,7 @@\n" "> \t\t\tenable-method = \"psci\";\n" "> \t\t\tnext-level-cache = <&A53_L2>;\n" @@ -103,7 +111,7 @@ "> +\t\t\tcapacity-dmips-mhz = <592>;\n" "> \t\t};\n" "> \n" - "> \t\tcpu4: cpu at 100 {\n" + "> \t\tcpu4: cpu@100 {\n" "> @@ -101,6 +105,7 @@\n" "> \t\t\t\t\t&CPU_SLEEP\n" "> \t\t\t\t\t&CLUSTER_SLEEP_1\n" @@ -111,7 +119,7 @@ "> +\t\t\tcapacity-dmips-mhz = <1024>;\n" "> \t\t};\n" "> \n" - "> \t\tcpu5: cpu at 101 {\n" + "> \t\tcpu5: cpu@101 {\n" "> @@ -114,6 +119,7 @@\n" "> \t\t\t\t\t&CPU_SLEEP\n" "> \t\t\t\t\t&CLUSTER_SLEEP_1\n" @@ -119,7 +127,7 @@ "> +\t\t\tcapacity-dmips-mhz = <1024>;\n" "> \t\t};\n" "> \n" - "> \t\tcpu6: cpu at 102 {\n" + "> \t\tcpu6: cpu@102 {\n" "> @@ -127,6 +133,7 @@\n" "> \t\t\t\t\t&CPU_SLEEP\n" "> \t\t\t\t\t&CLUSTER_SLEEP_1\n" @@ -127,7 +135,7 @@ "> +\t\t\tcapacity-dmips-mhz = <1024>;\n" "> \t\t};\n" "> \n" - "> \t\tcpu7: cpu at 103 {\n" + "> \t\tcpu7: cpu@103 {\n" "> @@ -140,6 +147,7 @@\n" "> \t\t\t\t\t&CPU_SLEEP\n" "> \t\t\t\t\t&CLUSTER_SLEEP_1\n" @@ -143,4 +151,4 @@ "> .\n" > -1142094e1018b4465e46088c75ad52d159d86e3575032169aab62106ef6868c1 +eba2108dfe5428a6ada32923cc24c5a39185c2e14739ba899537b293bbf4b918
diff --git a/a/1.txt b/N2/1.txt index a74fb82..7065489 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -72,7 +72,7 @@ Wei > + capacity-dmips-mhz = <592>; > }; > -> cpu1: cpu at 1 { +> cpu1: cpu@1 { > @@ -70,6 +71,7 @@ > enable-method = "psci"; > next-level-cache = <&A53_L2>; @@ -80,7 +80,7 @@ Wei > + capacity-dmips-mhz = <592>; > }; > -> cpu2: cpu at 2 { +> cpu2: cpu@2 { > @@ -79,6 +81,7 @@ > enable-method = "psci"; > next-level-cache = <&A53_L2>; @@ -88,7 +88,7 @@ Wei > + capacity-dmips-mhz = <592>; > }; > -> cpu3: cpu at 3 { +> cpu3: cpu@3 { > @@ -88,6 +91,7 @@ > enable-method = "psci"; > next-level-cache = <&A53_L2>; @@ -96,7 +96,7 @@ Wei > + capacity-dmips-mhz = <592>; > }; > -> cpu4: cpu at 100 { +> cpu4: cpu@100 { > @@ -101,6 +105,7 @@ > &CPU_SLEEP > &CLUSTER_SLEEP_1 @@ -104,7 +104,7 @@ Wei > + capacity-dmips-mhz = <1024>; > }; > -> cpu5: cpu at 101 { +> cpu5: cpu@101 { > @@ -114,6 +119,7 @@ > &CPU_SLEEP > &CLUSTER_SLEEP_1 @@ -112,7 +112,7 @@ Wei > + capacity-dmips-mhz = <1024>; > }; > -> cpu6: cpu at 102 { +> cpu6: cpu@102 { > @@ -127,6 +133,7 @@ > &CPU_SLEEP > &CLUSTER_SLEEP_1 @@ -120,7 +120,7 @@ Wei > + capacity-dmips-mhz = <1024>; > }; > -> cpu7: cpu at 103 { +> cpu7: cpu@103 { > @@ -140,6 +147,7 @@ > &CPU_SLEEP > &CLUSTER_SLEEP_1 diff --git a/a/content_digest b/N2/content_digest index 3242389..87acd55 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,8 +1,16 @@ "ref\01513174866-6678-1-git-send-email-valentin.schneider@arm.com\0" - "From\0xuwei5@hisilicon.com (Wei Xu)\0" - "Subject\0[PATCH] arm64: dts: hisilicon: Add hi3660 cpu capacity-dmips-mhz information\0" + "From\0Wei Xu <xuwei5@hisilicon.com>\0" + "Subject\0Re: [PATCH] arm64: dts: hisilicon: Add hi3660 cpu capacity-dmips-mhz information\0" "Date\0Fri, 22 Dec 2017 09:38:14 +0000\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Valentin Schneider <valentin.schneider@arm.com>" + " <linux-kernel@vger.kernel.org>\0" + "Cc\0Rob Herring <robh+dt@kernel.org>" + Mark Rutland <mark.rutland@arm.com> + Catalin Marinas <catalin.marinas@arm.com> + Will Deacon <will.deacon@arm.com> + Dietmar Eggemann <dietmar.eggemann@arm.com> + <linux-arm-kernel@lists.infradead.org> + " <devicetree@vger.kernel.org>\0" "\00:1\0" "b\0" "Hi Valentin,\n" @@ -79,7 +87,7 @@ "> +\t\t\tcapacity-dmips-mhz = <592>;\n" "> \t\t};\n" "> \n" - "> \t\tcpu1: cpu at 1 {\n" + "> \t\tcpu1: cpu@1 {\n" "> @@ -70,6 +71,7 @@\n" "> \t\t\tenable-method = \"psci\";\n" "> \t\t\tnext-level-cache = <&A53_L2>;\n" @@ -87,7 +95,7 @@ "> +\t\t\tcapacity-dmips-mhz = <592>;\n" "> \t\t};\n" "> \n" - "> \t\tcpu2: cpu at 2 {\n" + "> \t\tcpu2: cpu@2 {\n" "> @@ -79,6 +81,7 @@\n" "> \t\t\tenable-method = \"psci\";\n" "> \t\t\tnext-level-cache = <&A53_L2>;\n" @@ -95,7 +103,7 @@ "> +\t\t\tcapacity-dmips-mhz = <592>;\n" "> \t\t};\n" "> \n" - "> \t\tcpu3: cpu at 3 {\n" + "> \t\tcpu3: cpu@3 {\n" "> @@ -88,6 +91,7 @@\n" "> \t\t\tenable-method = \"psci\";\n" "> \t\t\tnext-level-cache = <&A53_L2>;\n" @@ -103,7 +111,7 @@ "> +\t\t\tcapacity-dmips-mhz = <592>;\n" "> \t\t};\n" "> \n" - "> \t\tcpu4: cpu at 100 {\n" + "> \t\tcpu4: cpu@100 {\n" "> @@ -101,6 +105,7 @@\n" "> \t\t\t\t\t&CPU_SLEEP\n" "> \t\t\t\t\t&CLUSTER_SLEEP_1\n" @@ -111,7 +119,7 @@ "> +\t\t\tcapacity-dmips-mhz = <1024>;\n" "> \t\t};\n" "> \n" - "> \t\tcpu5: cpu at 101 {\n" + "> \t\tcpu5: cpu@101 {\n" "> @@ -114,6 +119,7 @@\n" "> \t\t\t\t\t&CPU_SLEEP\n" "> \t\t\t\t\t&CLUSTER_SLEEP_1\n" @@ -119,7 +127,7 @@ "> +\t\t\tcapacity-dmips-mhz = <1024>;\n" "> \t\t};\n" "> \n" - "> \t\tcpu6: cpu at 102 {\n" + "> \t\tcpu6: cpu@102 {\n" "> @@ -127,6 +133,7 @@\n" "> \t\t\t\t\t&CPU_SLEEP\n" "> \t\t\t\t\t&CLUSTER_SLEEP_1\n" @@ -127,7 +135,7 @@ "> +\t\t\tcapacity-dmips-mhz = <1024>;\n" "> \t\t};\n" "> \n" - "> \t\tcpu7: cpu at 103 {\n" + "> \t\tcpu7: cpu@103 {\n" "> @@ -140,6 +147,7 @@\n" "> \t\t\t\t\t&CPU_SLEEP\n" "> \t\t\t\t\t&CLUSTER_SLEEP_1\n" @@ -143,4 +151,4 @@ "> .\n" > -1142094e1018b4465e46088c75ad52d159d86e3575032169aab62106ef6868c1 +7680a0484418f957a833c7a0069ba4db727d439aecc8b55d25d81eea21d08877
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