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From: "Zhang, Jerry (Junwei)" <Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
To: "Marek Olšák" <maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH libdrm] admgpu: add amdgpu_query_sw_info for querying high bits of 32-bit address space
Date: Mon, 5 Feb 2018 09:51:32 +0800	[thread overview]
Message-ID: <5A77B8A4.30409@amd.com> (raw)
In-Reply-To: <1517592891-25061-1-git-send-email-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

Just a typo in commit log:
admgpu -> amdgpu

Jerry

On 02/03/2018 01:34 AM, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak@amd.com>
>
> ---
>   amdgpu/amdgpu.h          | 21 +++++++++++++++++++++
>   amdgpu/amdgpu_device.c   | 14 ++++++++++++++
>   amdgpu/amdgpu_internal.h |  1 +
>   3 files changed, 36 insertions(+)
>
> diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
> index 2eb03bf..928b2a6 100644
> --- a/amdgpu/amdgpu.h
> +++ b/amdgpu/amdgpu.h
> @@ -87,20 +87,24 @@ enum amdgpu_bo_handle_type {
>   	amdgpu_bo_handle_type_dma_buf_fd = 2
>   };
>
>   /** Define known types of GPU VM VA ranges */
>   enum amdgpu_gpu_va_range
>   {
>   	/** Allocate from "normal"/general range */
>   	amdgpu_gpu_va_range_general = 0
>   };
>
> +enum amdgpu_sw_info {
> +	amdgpu_sw_info_address32_hi = 0,
> +};
> +
>   /*--------------------------------------------------------------------------*/
>   /* -------------------------- Datatypes ----------------------------------- */
>   /*--------------------------------------------------------------------------*/
>
>   /**
>    * Define opaque pointer to context associated with fd.
>    * This context will be returned as the result of
>    * "initialize" function and should be pass as the first
>    * parameter to any API call
>    */
> @@ -1079,20 +1083,37 @@ int amdgpu_query_gpu_info(amdgpu_device_handle dev,
>    * \param   value   - \c [out] Pointer to the return value.
>    *
>    * \return   0 on success\n
>    *          <0 - Negative POSIX error code
>    *
>   */
>   int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id,
>   		      unsigned size, void *value);
>
>   /**
> + * Query hardware or driver information.
> + *
> + * The return size is query-specific and depends on the "info_id" parameter.
> + * No more than "size" bytes is returned.
> + *
> + * \param   dev     - \c [in] Device handle. See #amdgpu_device_initialize()
> + * \param   info    - \c [in] amdgpu_sw_info_*
> + * \param   value   - \c [out] Pointer to the return value.
> + *
> + * \return   0 on success\n
> + *          <0 - Negative POSIX error code
> + *
> +*/
> +int amdgpu_query_sw_info(amdgpu_device_handle dev, enum amdgpu_sw_info info,
> +			 void *value);
> +
> +/**
>    * Query information about GDS
>    *
>    * \param   dev	     - \c [in] Device handle. See #amdgpu_device_initialize()
>    * \param   gds_info - \c [out] Pointer to structure to get GDS information
>    *
>    * \return   0 on success\n
>    *          <0 - Negative POSIX Error code
>    *
>   */
>   int amdgpu_query_gds_info(amdgpu_device_handle dev,
> diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c
> index f34e27a..6ee25a9 100644
> --- a/amdgpu/amdgpu_device.c
> +++ b/amdgpu/amdgpu_device.c
> @@ -268,20 +268,21 @@ int amdgpu_device_initialize(int fd,
>   		start = dev->dev_info.high_va_offset;
>   		max = dev->dev_info.high_va_max;
>   	} else {
>   		start = dev->dev_info.virtual_address_offset;
>   		max = dev->dev_info.virtual_address_max;
>   	}
>
>   	max = MIN2(max, (start & ~0xffffffffULL) + 0x100000000ULL);
>   	amdgpu_vamgr_init(&dev->vamgr_32, start, max,
>   			  dev->dev_info.virtual_address_alignment);
> +	dev->address32_hi = start >> 32;
>
>   	start = max;
>   	if (dev->dev_info.high_va_offset && dev->dev_info.high_va_max)
>   		max = dev->dev_info.high_va_max;
>   	else
>   		max = dev->dev_info.virtual_address_max;
>   	amdgpu_vamgr_init(&dev->vamgr, start, max,
>   			  dev->dev_info.virtual_address_alignment);
>
>   	amdgpu_parse_asic_ids(dev);
> @@ -305,10 +306,23 @@ cleanup:
>   int amdgpu_device_deinitialize(amdgpu_device_handle dev)
>   {
>   	amdgpu_device_reference(&dev, NULL);
>   	return 0;
>   }
>
>   const char *amdgpu_get_marketing_name(amdgpu_device_handle dev)
>   {
>   	return dev->marketing_name;
>   }
> +
> +int amdgpu_query_sw_info(amdgpu_device_handle dev, enum amdgpu_sw_info info,
> +			 void *value)
> +{
> +	uint32_t *val32 = (uint32_t*)value;
> +
> +	switch (info) {
> +	case amdgpu_sw_info_address32_hi:
> +		*val32 = dev->address32_hi;
> +		return 0;
> +	}
> +	return -EINVAL;
> +}
> diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h
> index 3e044f1..802b162 100644
> --- a/amdgpu/amdgpu_internal.h
> +++ b/amdgpu/amdgpu_internal.h
> @@ -68,20 +68,21 @@ struct amdgpu_va {
>   	enum amdgpu_gpu_va_range range;
>   	struct amdgpu_bo_va_mgr *vamgr;
>   };
>
>   struct amdgpu_device {
>   	atomic_t refcount;
>   	int fd;
>   	int flink_fd;
>   	unsigned major_version;
>   	unsigned minor_version;
> +	uint32_t address32_hi;
>
>   	char *marketing_name;
>   	/** List of buffer handles. Protected by bo_table_mutex. */
>   	struct util_hash_table *bo_handles;
>   	/** List of buffer GEM flink names. Protected by bo_table_mutex. */
>   	struct util_hash_table *bo_flink_names;
>   	/** This protects all hash tables. */
>   	pthread_mutex_t bo_table_mutex;
>   	struct drm_amdgpu_info_device dev_info;
>   	struct amdgpu_gpu_info info;
>
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      parent reply	other threads:[~2018-02-05  1:51 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-02 17:34 [PATCH libdrm] admgpu: add amdgpu_query_sw_info for querying high bits of 32-bit address space Marek Olšák
     [not found] ` <1517592891-25061-1-git-send-email-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-02-02 19:03   ` Christian König
2018-02-05  1:51   ` Zhang, Jerry (Junwei) [this message]

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