From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: MIME-version: 1.0 Content-type: text/plain; charset="UTF-8" Message-id: <5AA097FA.5070704@samsung.com> Date: Thu, 08 Mar 2018 10:55:06 +0900 From: Chanwoo Choi To: Sylwester Nawrocki , linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, b.zolnierkie@samsung.com, m.szyprowski@samsung.com Subject: Re: [PATCH] clk: samsung: exynos5420: Add more entries to EPLL rate table In-reply-to: <20180307164656.12194-2-s.nawrocki@samsung.com> References: <20180307164656.12194-1-s.nawrocki@samsung.com> <20180307164656.12194-2-s.nawrocki@samsung.com> List-ID: On 2018년 03월 08일 01:46, Sylwester Nawrocki wrote: > Adding these EPLL output frequency entries allows to support all required > audio sample rates on the CODEC and the HDMI interface on Peach-Pit > Chromebook. > > Signed-off-by: Sylwester Nawrocki > --- > drivers/clk/samsung/clk-exynos5420.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c > index 1f204ba37f0f..f2607cb97a97 100644 > --- a/drivers/clk/samsung/clk-exynos5420.c > +++ b/drivers/clk/samsung/clk-exynos5420.c > @@ -1360,8 +1360,11 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { > PLL_36XX_RATE(180633609U, 301, 5, 3, 3671), > PLL_36XX_RATE(131072006U, 131, 3, 3, 4719), > PLL_36XX_RATE(100000000U, 200, 3, 4, 0), > + PLL_36XX_RATE( 73728000U, 98, 2, 4, 19923), > + PLL_36XX_RATE( 67737602U, 90, 2, 4, 20762), > PLL_36XX_RATE( 65536003U, 131, 3, 4, 4719), > PLL_36XX_RATE( 49152000U, 197, 3, 5, -25690), > + PLL_36XX_RATE( 45158401U, 90, 3, 4, 20762), > PLL_36XX_RATE( 32768001U, 131, 3, 5, 4719), > }; > > Looks good to me. Acked-by: Chanwoo Choi -- Best Regards, Chanwoo Choi Samsung Electronics From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chanwoo Choi Subject: Re: [PATCH] clk: samsung: exynos5420: Add more entries to EPLL rate table Date: Thu, 08 Mar 2018 10:55:06 +0900 Message-ID: <5AA097FA.5070704@samsung.com> References: <20180307164656.12194-1-s.nawrocki@samsung.com> <20180307164656.12194-2-s.nawrocki@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-reply-to: <20180307164656.12194-2-s.nawrocki@samsung.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Sylwester Nawrocki , linux-clk@vger.kernel.org Cc: linux-samsung-soc@vger.kernel.org, b.zolnierkie@samsung.com, sboyd@kernel.org, mturquette@baylibre.com, linux-arm-kernel@lists.infradead.org, m.szyprowski@samsung.com List-Id: linux-samsung-soc@vger.kernel.org T24gMjAxOOuFhCAwM+yblCAwOOydvCAwMTo0NiwgU3lsd2VzdGVyIE5hd3JvY2tpIHdyb3RlOgo+ IEFkZGluZyB0aGVzZSBFUExMIG91dHB1dCBmcmVxdWVuY3kgZW50cmllcyBhbGxvd3MgdG8gc3Vw cG9ydCBhbGwgcmVxdWlyZWQKPiBhdWRpbyBzYW1wbGUgcmF0ZXMgb24gdGhlIENPREVDIGFuZCB0 aGUgSERNSSBpbnRlcmZhY2Ugb24gUGVhY2gtUGl0Cj4gQ2hyb21lYm9vay4KPiAKPiBTaWduZWQt b2ZmLWJ5OiBTeWx3ZXN0ZXIgTmF3cm9ja2kgPHMubmF3cm9ja2lAc2Ftc3VuZy5jb20+Cj4gLS0t Cj4gIGRyaXZlcnMvY2xrL3NhbXN1bmcvY2xrLWV4eW5vczU0MjAuYyB8IDMgKysrCj4gIDEgZmls ZSBjaGFuZ2VkLCAzIGluc2VydGlvbnMoKykKPiAKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9jbGsv c2Ftc3VuZy9jbGstZXh5bm9zNTQyMC5jIGIvZHJpdmVycy9jbGsvc2Ftc3VuZy9jbGstZXh5bm9z NTQyMC5jCj4gaW5kZXggMWYyMDRiYTM3ZjBmLi5mMjYwN2NiOTdhOTcgMTAwNjQ0Cj4gLS0tIGEv ZHJpdmVycy9jbGsvc2Ftc3VuZy9jbGstZXh5bm9zNTQyMC5jCj4gKysrIGIvZHJpdmVycy9jbGsv c2Ftc3VuZy9jbGstZXh5bm9zNTQyMC5jCj4gQEAgLTEzNjAsOCArMTM2MCwxMSBAQCBzdGF0aWMg Y29uc3Qgc3RydWN0IHNhbXN1bmdfcGxsX3JhdGVfdGFibGUgZXh5bm9zNTQyMF9lcGxsXzI0bWh6 X3RibFtdID0gewo+ICAJUExMXzM2WFhfUkFURSgxODA2MzM2MDlVLCAzMDEsIDUsIDMsIDM2NzEp LAo+ICAJUExMXzM2WFhfUkFURSgxMzEwNzIwMDZVLCAxMzEsIDMsIDMsIDQ3MTkpLAo+ICAJUExM XzM2WFhfUkFURSgxMDAwMDAwMDBVLCAyMDAsIDMsIDQsIDApLAo+ICsJUExMXzM2WFhfUkFURSgg NzM3MjgwMDBVLCA5OCwgMiwgNCwgMTk5MjMpLAo+ICsJUExMXzM2WFhfUkFURSggNjc3Mzc2MDJV LCA5MCwgMiwgNCwgMjA3NjIpLAo+ICAJUExMXzM2WFhfUkFURSggNjU1MzYwMDNVLCAxMzEsIDMs IDQsIDQ3MTkpLAo+ICAJUExMXzM2WFhfUkFURSggNDkxNTIwMDBVLCAxOTcsIDMsIDUsIC0yNTY5 MCksCj4gKwlQTExfMzZYWF9SQVRFKCA0NTE1ODQwMVUsIDkwLCAzLCA0LCAyMDc2MiksCj4gIAlQ TExfMzZYWF9SQVRFKCAzMjc2ODAwMVUsIDEzMSwgMywgNSwgNDcxOSksCj4gIH07Cj4gIAo+IAoK TG9va3MgZ29vZCB0byBtZS4KQWNrZWQtYnk6IENoYW53b28gQ2hvaSA8Y3cwMC5jaG9pQHNhbXN1 bmcuY29tPgoKLS0gCkJlc3QgUmVnYXJkcywKQ2hhbndvbyBDaG9pClNhbXN1bmcgRWxlY3Ryb25p Y3MKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmxpbnV4 LWFybS1rZXJuZWwgbWFpbGluZyBsaXN0CmxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5mcmFkZWFk Lm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LWFy bS1rZXJuZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 From: cw00.choi@samsung.com (Chanwoo Choi) Date: Thu, 08 Mar 2018 10:55:06 +0900 Subject: [PATCH] clk: samsung: exynos5420: Add more entries to EPLL rate table In-Reply-To: <20180307164656.12194-2-s.nawrocki@samsung.com> References: <20180307164656.12194-1-s.nawrocki@samsung.com> <20180307164656.12194-2-s.nawrocki@samsung.com> Message-ID: <5AA097FA.5070704@samsung.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 2018? 03? 08? 01:46, Sylwester Nawrocki wrote: > Adding these EPLL output frequency entries allows to support all required > audio sample rates on the CODEC and the HDMI interface on Peach-Pit > Chromebook. > > Signed-off-by: Sylwester Nawrocki > --- > drivers/clk/samsung/clk-exynos5420.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c > index 1f204ba37f0f..f2607cb97a97 100644 > --- a/drivers/clk/samsung/clk-exynos5420.c > +++ b/drivers/clk/samsung/clk-exynos5420.c > @@ -1360,8 +1360,11 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { > PLL_36XX_RATE(180633609U, 301, 5, 3, 3671), > PLL_36XX_RATE(131072006U, 131, 3, 3, 4719), > PLL_36XX_RATE(100000000U, 200, 3, 4, 0), > + PLL_36XX_RATE( 73728000U, 98, 2, 4, 19923), > + PLL_36XX_RATE( 67737602U, 90, 2, 4, 20762), > PLL_36XX_RATE( 65536003U, 131, 3, 4, 4719), > PLL_36XX_RATE( 49152000U, 197, 3, 5, -25690), > + PLL_36XX_RATE( 45158401U, 90, 3, 4, 20762), > PLL_36XX_RATE( 32768001U, 131, 3, 5, 4719), > }; > > Looks good to me. Acked-by: Chanwoo Choi -- Best Regards, Chanwoo Choi Samsung Electronics