diff for duplicates of <5AEC8002.5000309@kontron.com> diff --git a/a/1.txt b/N1/1.txt index 4eb1015..f4d9c59 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,9 +1,8 @@ -Le 04/05/2018 00:31, Bjorn Helgaas a =E9crit : +Le 04/05/2018 00:31, Bjorn Helgaas a ?crit : > [+cc LKML] > > On Thu, May 03, 2018 at 12:40:27PM +0000, Gilles Buloz wrote: ->> Subject: [PATCH] For exception at PCI probe due to bridge reporting U= -R +>> Subject: [PATCH] For exception at PCI probe due to bridge reporting UR >> >> Even if a device supports extended config access, no such access must be >> done to this device If there's a bridge not supporting that in the path @@ -20,16 +19,13 @@ R >> -> PCI-to-PCIe bridge >> -> PCIe switch (4 ports) >> -> 4 PCIe devices (one on each port) ->> In this case all devices behind the PEX8112 are supporting extended conf= -ig +>> In this case all devices behind the PEX8112 are supporting extended config >> access but this is prohibited by the PEX8112. Without this patch, an >> exception (synchronous abort) occurs in pci_cfg_space_size_ext(). >> ->> This patch checks the parent bridge of each allocated child bus to know = -if +>> This patch checks the parent bridge of each allocated child bus to know if >> extended config access is supported on the child bus, and sets a flag in ->> child->bus_flags if not supported. This flag is inherited by all childr= -en +>> child->bus_flags if not supported. This flag is inherited by all children >> buses of this child bus and then is checked to avoid this unsupported >> accesses to every device on these buses. > Hi Gilles, @@ -40,8 +36,7 @@ en > Hi Bjorn, -Your rework works as expected. Tested on LS1043A platform with kernel 4.17-= -rc1, and with some backport on kernel 4.1.35 +Your rework works as expected. Tested on LS1043A platform with kernel 4.17-rc1, and with some backport on kernel 4.1.35 Suggestion : maybe change the pci_info() string to have : pci_bus 0000:xx: extended config space not accessible @@ -49,19 +44,14 @@ instead of pci_bus 0000:xx: extended config space not accessible on secondary bus as xx is already the number of the secondary bus -Info : with kernel 4.17-rc1, it turns out I need pcie_aspm=3Doff to have th= -e PMC devices behind the -PCI-to-PCIe bridge of the PMC safely detected/configured. But this is not c= -aused by the patch. -Without pcie_aspm=3Doff I saw this at one boot : - "pci 0000:02:0e.0: ASPM: Could not configure common clock" for this bri= -dge, but devices +Info : with kernel 4.17-rc1, it turns out I need pcie_aspm=off to have the PMC devices behind the +PCI-to-PCIe bridge of the PMC safely detected/configured. But this is not caused by the patch. +Without pcie_aspm=off I saw this at one boot : + "pci 0000:02:0e.0: ASPM: Could not configure common clock" for this bridge, but devices correctly detected/configured but at most boots I get : - no ASPM message but "pci 0000:04:02.0: bridge configuration invalid ([b= -us ff-ff]), reconfiguring " - instead, and some devices are missing. Also lspci show "rev ff" for som= -e devices. + no ASPM message but "pci 0000:04:02.0: bridge configuration invalid ([bus ff-ff]), reconfiguring " + instead, and some devices are missing. Also lspci show "rev ff" for some devices. I don't see this problem on 4.1.35 with the same backported patch. Gilles @@ -70,59 +60,46 @@ Gilles > Date: Thu May 3 15:21:44 2018 -0500 > > PCI: Check whether bridges allow access to extended config space -> =20 -> Even if a device supports extended config space, i.e., it is a PCI-X= - Mode 2 +> +> Even if a device supports extended config space, i.e., it is a PCI-X Mode 2 > or a PCI Express device, the extended space may not be accessible if > there's a conventional PCI bus in the path to it. -> =20 -> We currently figure that out in pci_cfg_space_size() by reading the = -first -> dword of extended config space. On most platforms that returns ~0 d= -ata if +> +> We currently figure that out in pci_cfg_space_size() by reading the first +> dword of extended config space. On most platforms that returns ~0 data if > the space is inaccessible, but it may set error bits in PCI status -> registers, and on some platforms it causes exceptions that we curren= -tly +> registers, and on some platforms it causes exceptions that we currently > don't recover from. -> =20 -> For example, a PCIe-to-conventional PCI bridge treats config transac= -tions -> with a non-zero Extended Register Address as an Unsupported Request = -on PCIe -> and a received Master-Abort on the destination bus (see PCI Express = -to +> +> For example, a PCIe-to-conventional PCI bridge treats config transactions +> with a non-zero Extended Register Address as an Unsupported Request on PCIe +> and a received Master-Abort on the destination bus (see PCI Express to > PCI/PCI-X Bridge spec, r1.0, sec 4.1.3). -> =20 -> A sample case is a LS1043A CPU (NXP QorIQ Layerscape) platform with = -the +> +> A sample case is a LS1043A CPU (NXP QorIQ Layerscape) platform with the > following bus topology: -> =20 +> > LS1043 PCIe Root Port -> -> PEX8112 PCIe-to-PCI bridge (doesn't support ext cfg on PCI si= -de) +> -> PEX8112 PCIe-to-PCI bridge (doesn't support ext cfg on PCI side) > -> PMC slot connector (for legacy PMC modules) -> =20 +> > With a PMC module topology as follows: -> =20 +> > PMC connector > -> PCI-to-PCIe bridge > -> PCIe switch (4 ports) > -> 4 PCIe devices (one on each port) -> =20 -> The PCIe devices on the PMC module support extended config space, bu= -t we -> can't reach it because the PEX8112 can't generate accesses to the ex= -tended +> +> The PCIe devices on the PMC module support extended config space, but we +> can't reach it because the PEX8112 can't generate accesses to the extended > space on its secondary bus. Attempts to access it cause Unsupported > Request errors, which result in synchronous aborts on this platform. -> =20 -> To avoid these errors, check whether bridges are capable of generati= -ng -> extended config space addresses on their secondary interfaces. If t= -hey +> +> To avoid these errors, check whether bridges are capable of generating +> extended config space addresses on their secondary interfaces. If they > can't, we restrict devices below the bridge to only the 256-byte > PCI-compatible config space. -> =20 +> > Signed-off-by: Gilles Buloz <gilles.buloz@kontron.com> > [bhelgaas: changelog, rework patch so bus_flags testing is all in > pci_bridge_child_ext_cfg_accessible()] @@ -132,93 +109,90 @@ hey > index ac91b6fd0bcd..7b1b7b2e01e4 100644 > --- a/drivers/pci/probe.c > +++ b/drivers/pci/probe.c -> @@ -882,6 +882,45 @@ static int pci_register_host_bridge(struct pci_host_= -bridge *bridge) -> =09return err; +> @@ -882,6 +882,45 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge) +> return err; > } -> =20 +> > +static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge) > +{ -> +=09int pos; -> +=09u32 status; +> + int pos; +> + u32 status; > + -> +=09/* -> +=09 * If extended config space isn't accessible on a bridge's primary -> +=09 * bus, we certainly can't access it on the secondary bus. -> +=09 */ -> +=09if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) -> +=09=09return false; +> + /* +> + * If extended config space isn't accessible on a bridge's primary +> + * bus, we certainly can't access it on the secondary bus. +> + */ +> + if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) +> + return false; > + -> +=09/* -> +=09 * PCIe Root Ports and switch ports are PCIe on both sides, so if -> +=09 * extended config space is accessible on the primary, it's also -> +=09 * accessible on the secondary. -> +=09 */ -> +=09if (pci_is_pcie(bridge) && -> +=09 (pci_pcie_type(bridge) =3D=3D PCI_EXP_TYPE_ROOT_PORT || -> +=09 pci_pcie_type(bridge) =3D=3D PCI_EXP_TYPE_UPSTREAM || -> +=09 pci_pcie_type(bridge) =3D=3D PCI_EXP_TYPE_DOWNSTREAM)) -> +=09=09return true; +> + /* +> + * PCIe Root Ports and switch ports are PCIe on both sides, so if +> + * extended config space is accessible on the primary, it's also +> + * accessible on the secondary. +> + */ +> + if (pci_is_pcie(bridge) && +> + (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT || +> + pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM || +> + pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM)) +> + return true; > + -> +=09/* -> +=09 * For the other bridge types: -> +=09 * - PCI-to-PCI bridges -> +=09 * - PCIe-to-PCI/PCI-X forward bridges -> +=09 * - PCI/PCI-X-to-PCIe reverse bridges -> +=09 * extended config space on the secondary side is only accessible -> +=09 * if the bridge supports PCI-X Mode 2. -> +=09 */ -> +=09pos =3D pci_find_capability(bridge, PCI_CAP_ID_PCIX); -> +=09if (!pos) -> +=09=09return false; +> + /* +> + * For the other bridge types: +> + * - PCI-to-PCI bridges +> + * - PCIe-to-PCI/PCI-X forward bridges +> + * - PCI/PCI-X-to-PCIe reverse bridges +> + * extended config space on the secondary side is only accessible +> + * if the bridge supports PCI-X Mode 2. +> + */ +> + pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); +> + if (!pos) +> + return false; > + -> +=09pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status); -> +=09return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ); +> + pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status); +> + return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ); > +} > + > static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, -> =09=09=09=09=09 struct pci_dev *bridge, int busnr) +> struct pci_dev *bridge, int busnr) > { -> @@ -923,6 +962,16 @@ static struct pci_bus *pci_alloc_child_bus(struct pc= -i_bus *parent, -> =09pci_set_bus_of_node(child); -> =09pci_set_bus_speed(child); -> =20 -> +=09/* -> +=09 * Check whether extended config space is accessible on the child -> +=09 * bus. Note that we currently assume it is always accessible on -> +=09 * the root bus. -> +=09 */ -> +=09if (!pci_bridge_child_ext_cfg_accessible(bridge)) { -> +=09=09child->bus_flags |=3D PCI_BUS_FLAGS_NO_EXTCFG; -> +=09=09pci_info(child, "extended config space not accessible on secondary= - bus\n"); -> +=09} +> @@ -923,6 +962,16 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, +> pci_set_bus_of_node(child); +> pci_set_bus_speed(child); +> +> + /* +> + * Check whether extended config space is accessible on the child +> + * bus. Note that we currently assume it is always accessible on +> + * the root bus. +> + */ +> + if (!pci_bridge_child_ext_cfg_accessible(bridge)) { +> + child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG; +> + pci_info(child, "extended config space not accessible on secondary bus\n"); +> + } > + -> =09/* Set up default resource pointers and names */ -> =09for (i =3D 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { -> =09=09child->resource[i] =3D &bridge->resource[PCI_BRIDGE_RESOURCES+i]; +> /* Set up default resource pointers and names */ +> for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { +> child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; > @@ -1393,6 +1442,9 @@ int pci_cfg_space_size(struct pci_dev *dev) -> =09u32 status; -> =09u16 class; -> =20 -> +=09if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) -> +=09=09return PCI_CFG_SPACE_SIZE; +> u32 status; +> u16 class; +> +> + if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) +> + return PCI_CFG_SPACE_SIZE; > + -> =09class =3D dev->class >> 8; -> =09if (class =3D=3D PCI_CLASS_BRIDGE_HOST) -> =09=09return pci_cfg_space_size_ext(dev); +> class = dev->class >> 8; +> if (class == PCI_CLASS_BRIDGE_HOST) +> return pci_cfg_space_size_ext(dev); > diff --git a/include/linux/pci.h b/include/linux/pci.h > index 230615620a4a..f7aa6d9f8999 100644 > --- a/include/linux/pci.h > +++ b/include/linux/pci.h > @@ -217,6 +217,7 @@ enum pci_bus_flags { -> =09PCI_BUS_FLAGS_NO_MSI=09=3D (__force pci_bus_flags_t) 1, -> =09PCI_BUS_FLAGS_NO_MMRBC=09=3D (__force pci_bus_flags_t) 2, -> =09PCI_BUS_FLAGS_NO_AERSID=09=3D (__force pci_bus_flags_t) 4, -> +=09PCI_BUS_FLAGS_NO_EXTCFG=09=3D (__force pci_bus_flags_t) 8, +> PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, +> PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, +> PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, +> + PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, > }; -> =20 +> > /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ > > . diff --git a/a/content_digest b/N1/content_digest index f142e30..4bbc014 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -9,24 +9,17 @@ "ref\020180502172341.GA123831@bhelgaas-glaptop.roam.corp.google.com\0" "ref\05AEB033A.4060407@kontron.com\0" "ref\020180503223127.GB15790@bhelgaas-glaptop.roam.corp.google.com\0" - "From\0Gilles Buloz <Gilles.Buloz@kontron.com>\0" - "Subject\0Re: [PATCH] PCI: Check whether bridges allow access to extended config space\0" + "From\0Gilles.Buloz@kontron.com (Gilles Buloz)\0" + "Subject\0[PATCH] PCI: Check whether bridges allow access to extended config space\0" "Date\0Fri, 4 May 2018 15:45:07 +0000\0" - "To\0Bjorn Helgaas <helgaas@kernel.org>\0" - "Cc\0Bjorn Helgaas <bhelgaas@google.com>" - linux-pci <linux-pci@vger.kernel.org> - Minghuan.Lian@nxp.com <Minghuan.Lian@nxp.com> - linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> - Ard Biesheuvel <ard.biesheuvel@linaro.org> - " linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" - "Le 04/05/2018 00:31, Bjorn Helgaas a =E9crit :\n" + "Le 04/05/2018 00:31, Bjorn Helgaas a ?crit :\n" "> [+cc LKML]\n" ">\n" "> On Thu, May 03, 2018 at 12:40:27PM +0000, Gilles Buloz wrote:\n" - ">> Subject: [PATCH] For exception at PCI probe due to bridge reporting U=\n" - "R\n" + ">> Subject: [PATCH] For exception at PCI probe due to bridge reporting UR\n" ">>\n" ">> Even if a device supports extended config access, no such access must be\n" ">> done to this device If there's a bridge not supporting that in the path\n" @@ -43,16 +36,13 @@ ">> -> PCI-to-PCIe bridge\n" ">> -> PCIe switch (4 ports)\n" ">> -> 4 PCIe devices (one on each port)\n" - ">> In this case all devices behind the PEX8112 are supporting extended conf=\n" - "ig\n" + ">> In this case all devices behind the PEX8112 are supporting extended config\n" ">> access but this is prohibited by the PEX8112. Without this patch, an\n" ">> exception (synchronous abort) occurs in pci_cfg_space_size_ext().\n" ">>\n" - ">> This patch checks the parent bridge of each allocated child bus to know =\n" - "if\n" + ">> This patch checks the parent bridge of each allocated child bus to know if\n" ">> extended config access is supported on the child bus, and sets a flag in\n" - ">> child->bus_flags if not supported. This flag is inherited by all childr=\n" - "en\n" + ">> child->bus_flags if not supported. This flag is inherited by all children\n" ">> buses of this child bus and then is checked to avoid this unsupported\n" ">> accesses to every device on these buses.\n" "> Hi Gilles,\n" @@ -63,8 +53,7 @@ ">\n" "Hi Bjorn,\n" "\n" - "Your rework works as expected. Tested on LS1043A platform with kernel 4.17-=\n" - "rc1, and with some backport on kernel 4.1.35\n" + "Your rework works as expected. Tested on LS1043A platform with kernel 4.17-rc1, and with some backport on kernel 4.1.35\n" "\n" "Suggestion : maybe change the pci_info() string to have :\n" " pci_bus 0000:xx: extended config space not accessible\n" @@ -72,19 +61,14 @@ " pci_bus 0000:xx: extended config space not accessible on secondary bus\n" "as xx is already the number of the secondary bus\n" "\n" - "Info : with kernel 4.17-rc1, it turns out I need pcie_aspm=3Doff to have th=\n" - "e PMC devices behind the\n" - "PCI-to-PCIe bridge of the PMC safely detected/configured. But this is not c=\n" - "aused by the patch.\n" - "Without pcie_aspm=3Doff I saw this at one boot :\n" - " \"pci 0000:02:0e.0: ASPM: Could not configure common clock\" for this bri=\n" - "dge, but devices\n" + "Info : with kernel 4.17-rc1, it turns out I need pcie_aspm=off to have the PMC devices behind the\n" + "PCI-to-PCIe bridge of the PMC safely detected/configured. But this is not caused by the patch.\n" + "Without pcie_aspm=off I saw this at one boot :\n" + " \"pci 0000:02:0e.0: ASPM: Could not configure common clock\" for this bridge, but devices\n" " correctly detected/configured\n" "but at most boots I get :\n" - " no ASPM message but \"pci 0000:04:02.0: bridge configuration invalid ([b=\n" - "us ff-ff]), reconfiguring \"\n" - " instead, and some devices are missing. Also lspci show \"rev ff\" for som=\n" - "e devices.\n" + " no ASPM message but \"pci 0000:04:02.0: bridge configuration invalid ([bus ff-ff]), reconfiguring \"\n" + " instead, and some devices are missing. Also lspci show \"rev ff\" for some devices.\n" "I don't see this problem on 4.1.35 with the same backported patch.\n" "\n" "Gilles\n" @@ -93,59 +77,46 @@ "> Date: Thu May 3 15:21:44 2018 -0500\n" ">\n" "> PCI: Check whether bridges allow access to extended config space\n" - "> =20\n" - "> Even if a device supports extended config space, i.e., it is a PCI-X=\n" - " Mode 2\n" + "> \n" + "> Even if a device supports extended config space, i.e., it is a PCI-X Mode 2\n" "> or a PCI Express device, the extended space may not be accessible if\n" "> there's a conventional PCI bus in the path to it.\n" - "> =20\n" - "> We currently figure that out in pci_cfg_space_size() by reading the =\n" - "first\n" - "> dword of extended config space. On most platforms that returns ~0 d=\n" - "ata if\n" + "> \n" + "> We currently figure that out in pci_cfg_space_size() by reading the first\n" + "> dword of extended config space. On most platforms that returns ~0 data if\n" "> the space is inaccessible, but it may set error bits in PCI status\n" - "> registers, and on some platforms it causes exceptions that we curren=\n" - "tly\n" + "> registers, and on some platforms it causes exceptions that we currently\n" "> don't recover from.\n" - "> =20\n" - "> For example, a PCIe-to-conventional PCI bridge treats config transac=\n" - "tions\n" - "> with a non-zero Extended Register Address as an Unsupported Request =\n" - "on PCIe\n" - "> and a received Master-Abort on the destination bus (see PCI Express =\n" - "to\n" + "> \n" + "> For example, a PCIe-to-conventional PCI bridge treats config transactions\n" + "> with a non-zero Extended Register Address as an Unsupported Request on PCIe\n" + "> and a received Master-Abort on the destination bus (see PCI Express to\n" "> PCI/PCI-X Bridge spec, r1.0, sec 4.1.3).\n" - "> =20\n" - "> A sample case is a LS1043A CPU (NXP QorIQ Layerscape) platform with =\n" - "the\n" + "> \n" + "> A sample case is a LS1043A CPU (NXP QorIQ Layerscape) platform with the\n" "> following bus topology:\n" - "> =20\n" + "> \n" "> LS1043 PCIe Root Port\n" - "> -> PEX8112 PCIe-to-PCI bridge (doesn't support ext cfg on PCI si=\n" - "de)\n" + "> -> PEX8112 PCIe-to-PCI bridge (doesn't support ext cfg on PCI side)\n" "> -> PMC slot connector (for legacy PMC modules)\n" - "> =20\n" + "> \n" "> With a PMC module topology as follows:\n" - "> =20\n" + "> \n" "> PMC connector\n" "> -> PCI-to-PCIe bridge\n" "> -> PCIe switch (4 ports)\n" "> -> 4 PCIe devices (one on each port)\n" - "> =20\n" - "> The PCIe devices on the PMC module support extended config space, bu=\n" - "t we\n" - "> can't reach it because the PEX8112 can't generate accesses to the ex=\n" - "tended\n" + "> \n" + "> The PCIe devices on the PMC module support extended config space, but we\n" + "> can't reach it because the PEX8112 can't generate accesses to the extended\n" "> space on its secondary bus. Attempts to access it cause Unsupported\n" "> Request errors, which result in synchronous aborts on this platform.\n" - "> =20\n" - "> To avoid these errors, check whether bridges are capable of generati=\n" - "ng\n" - "> extended config space addresses on their secondary interfaces. If t=\n" - "hey\n" + "> \n" + "> To avoid these errors, check whether bridges are capable of generating\n" + "> extended config space addresses on their secondary interfaces. If they\n" "> can't, we restrict devices below the bridge to only the 256-byte\n" "> PCI-compatible config space.\n" - "> =20\n" + "> \n" "> Signed-off-by: Gilles Buloz <gilles.buloz@kontron.com>\n" "> [bhelgaas: changelog, rework patch so bus_flags testing is all in\n" "> pci_bridge_child_ext_cfg_accessible()]\n" @@ -155,96 +126,93 @@ "> index ac91b6fd0bcd..7b1b7b2e01e4 100644\n" "> --- a/drivers/pci/probe.c\n" "> +++ b/drivers/pci/probe.c\n" - "> @@ -882,6 +882,45 @@ static int pci_register_host_bridge(struct pci_host_=\n" - "bridge *bridge)\n" - "> =09return err;\n" + "> @@ -882,6 +882,45 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge)\n" + "> \treturn err;\n" "> }\n" - "> =20\n" + "> \n" "> +static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)\n" "> +{\n" - "> +=09int pos;\n" - "> +=09u32 status;\n" + "> +\tint pos;\n" + "> +\tu32 status;\n" "> +\n" - "> +=09/*\n" - "> +=09 * If extended config space isn't accessible on a bridge's primary\n" - "> +=09 * bus, we certainly can't access it on the secondary bus.\n" - "> +=09 */\n" - "> +=09if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)\n" - "> +=09=09return false;\n" + "> +\t/*\n" + "> +\t * If extended config space isn't accessible on a bridge's primary\n" + "> +\t * bus, we certainly can't access it on the secondary bus.\n" + "> +\t */\n" + "> +\tif (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)\n" + "> +\t\treturn false;\n" "> +\n" - "> +=09/*\n" - "> +=09 * PCIe Root Ports and switch ports are PCIe on both sides, so if\n" - "> +=09 * extended config space is accessible on the primary, it's also\n" - "> +=09 * accessible on the secondary.\n" - "> +=09 */\n" - "> +=09if (pci_is_pcie(bridge) &&\n" - "> +=09 (pci_pcie_type(bridge) =3D=3D PCI_EXP_TYPE_ROOT_PORT ||\n" - "> +=09 pci_pcie_type(bridge) =3D=3D PCI_EXP_TYPE_UPSTREAM ||\n" - "> +=09 pci_pcie_type(bridge) =3D=3D PCI_EXP_TYPE_DOWNSTREAM))\n" - "> +=09=09return true;\n" + "> +\t/*\n" + "> +\t * PCIe Root Ports and switch ports are PCIe on both sides, so if\n" + "> +\t * extended config space is accessible on the primary, it's also\n" + "> +\t * accessible on the secondary.\n" + "> +\t */\n" + "> +\tif (pci_is_pcie(bridge) &&\n" + "> +\t (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||\n" + "> +\t pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||\n" + "> +\t pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))\n" + "> +\t\treturn true;\n" "> +\n" - "> +=09/*\n" - "> +=09 * For the other bridge types:\n" - "> +=09 * - PCI-to-PCI bridges\n" - "> +=09 * - PCIe-to-PCI/PCI-X forward bridges\n" - "> +=09 * - PCI/PCI-X-to-PCIe reverse bridges\n" - "> +=09 * extended config space on the secondary side is only accessible\n" - "> +=09 * if the bridge supports PCI-X Mode 2.\n" - "> +=09 */\n" - "> +=09pos =3D pci_find_capability(bridge, PCI_CAP_ID_PCIX);\n" - "> +=09if (!pos)\n" - "> +=09=09return false;\n" + "> +\t/*\n" + "> +\t * For the other bridge types:\n" + "> +\t * - PCI-to-PCI bridges\n" + "> +\t * - PCIe-to-PCI/PCI-X forward bridges\n" + "> +\t * - PCI/PCI-X-to-PCIe reverse bridges\n" + "> +\t * extended config space on the secondary side is only accessible\n" + "> +\t * if the bridge supports PCI-X Mode 2.\n" + "> +\t */\n" + "> +\tpos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);\n" + "> +\tif (!pos)\n" + "> +\t\treturn false;\n" "> +\n" - "> +=09pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);\n" - "> +=09return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);\n" + "> +\tpci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);\n" + "> +\treturn status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);\n" "> +}\n" "> +\n" "> static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,\n" - "> =09=09=09=09=09 struct pci_dev *bridge, int busnr)\n" + "> \t\t\t\t\t struct pci_dev *bridge, int busnr)\n" "> {\n" - "> @@ -923,6 +962,16 @@ static struct pci_bus *pci_alloc_child_bus(struct pc=\n" - "i_bus *parent,\n" - "> =09pci_set_bus_of_node(child);\n" - "> =09pci_set_bus_speed(child);\n" - "> =20\n" - "> +=09/*\n" - "> +=09 * Check whether extended config space is accessible on the child\n" - "> +=09 * bus. Note that we currently assume it is always accessible on\n" - "> +=09 * the root bus.\n" - "> +=09 */\n" - "> +=09if (!pci_bridge_child_ext_cfg_accessible(bridge)) {\n" - "> +=09=09child->bus_flags |=3D PCI_BUS_FLAGS_NO_EXTCFG;\n" - "> +=09=09pci_info(child, \"extended config space not accessible on secondary=\n" - " bus\\n\");\n" - "> +=09}\n" + "> @@ -923,6 +962,16 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,\n" + "> \tpci_set_bus_of_node(child);\n" + "> \tpci_set_bus_speed(child);\n" + "> \n" + "> +\t/*\n" + "> +\t * Check whether extended config space is accessible on the child\n" + "> +\t * bus. Note that we currently assume it is always accessible on\n" + "> +\t * the root bus.\n" + "> +\t */\n" + "> +\tif (!pci_bridge_child_ext_cfg_accessible(bridge)) {\n" + "> +\t\tchild->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;\n" + "> +\t\tpci_info(child, \"extended config space not accessible on secondary bus\\n\");\n" + "> +\t}\n" "> +\n" - "> =09/* Set up default resource pointers and names */\n" - "> =09for (i =3D 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {\n" - "> =09=09child->resource[i] =3D &bridge->resource[PCI_BRIDGE_RESOURCES+i];\n" + "> \t/* Set up default resource pointers and names */\n" + "> \tfor (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {\n" + "> \t\tchild->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];\n" "> @@ -1393,6 +1442,9 @@ int pci_cfg_space_size(struct pci_dev *dev)\n" - "> =09u32 status;\n" - "> =09u16 class;\n" - "> =20\n" - "> +=09if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)\n" - "> +=09=09return PCI_CFG_SPACE_SIZE;\n" + "> \tu32 status;\n" + "> \tu16 class;\n" + "> \n" + "> +\tif (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)\n" + "> +\t\treturn PCI_CFG_SPACE_SIZE;\n" "> +\n" - "> =09class =3D dev->class >> 8;\n" - "> =09if (class =3D=3D PCI_CLASS_BRIDGE_HOST)\n" - "> =09=09return pci_cfg_space_size_ext(dev);\n" + "> \tclass = dev->class >> 8;\n" + "> \tif (class == PCI_CLASS_BRIDGE_HOST)\n" + "> \t\treturn pci_cfg_space_size_ext(dev);\n" "> diff --git a/include/linux/pci.h b/include/linux/pci.h\n" "> index 230615620a4a..f7aa6d9f8999 100644\n" "> --- a/include/linux/pci.h\n" "> +++ b/include/linux/pci.h\n" "> @@ -217,6 +217,7 @@ enum pci_bus_flags {\n" - "> =09PCI_BUS_FLAGS_NO_MSI=09=3D (__force pci_bus_flags_t) 1,\n" - "> =09PCI_BUS_FLAGS_NO_MMRBC=09=3D (__force pci_bus_flags_t) 2,\n" - "> =09PCI_BUS_FLAGS_NO_AERSID=09=3D (__force pci_bus_flags_t) 4,\n" - "> +=09PCI_BUS_FLAGS_NO_EXTCFG=09=3D (__force pci_bus_flags_t) 8,\n" + "> \tPCI_BUS_FLAGS_NO_MSI\t= (__force pci_bus_flags_t) 1,\n" + "> \tPCI_BUS_FLAGS_NO_MMRBC\t= (__force pci_bus_flags_t) 2,\n" + "> \tPCI_BUS_FLAGS_NO_AERSID\t= (__force pci_bus_flags_t) 4,\n" + "> +\tPCI_BUS_FLAGS_NO_EXTCFG\t= (__force pci_bus_flags_t) 8,\n" "> };\n" - "> =20\n" + "> \n" "> /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */\n" ">\n" "> .\n" > -9798de9fd95955498c280257909aa7aea9decbd8c8db5f5d80751abf6b7198aa +83ad5d022a75f1b7a3eb0ab7eb7ea79ceb5beccd895b08219392ee70c1279884
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