diff for duplicates of <5AF5A16C.6090804@hisilicon.com> diff --git a/a/1.txt b/N1/1.txt index 4971ef5..5125fc6 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -68,7 +68,7 @@ Wei > #reset-cells = <2>; > }; > -> + perictrl: peripheral-controller at 8a20000 { +> + perictrl: peripheral-controller@8a20000 { > + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", > + "simple-mfd"; > + reg = <0x8a20000 0x1000>; @@ -76,7 +76,7 @@ Wei > + #size-cells = <1>; > + ranges = <0x0 0x8a20000 0x1000>; > + -> + combphy0: phy at 850 { +> + combphy0: phy@850 { > + compatible = "hisilicon,hi3798cv200-combphy"; > + reg = <0x850 0x8>; > + #phy-cells = <1>; @@ -87,7 +87,7 @@ Wei > + hisilicon,fixed-mode = <PHY_TYPE_USB3>; > + }; > + -> + combphy1: phy at 858 { +> + combphy1: phy@858 { > + compatible = "hisilicon,hi3798cv200-combphy"; > + reg = <0x858 0x8>; > + #phy-cells = <1>; @@ -99,7 +99,7 @@ Wei > + }; > + }; > + -> uart0: serial at 8b00000 { +> uart0: serial@8b00000 { > compatible = "arm,pl011", "arm,primecell"; > reg = <0x8b00000 0x1000>; > @@ -419,5 +452,35 @@ @@ -107,7 +107,7 @@ Wei > status = "disabled"; > }; > + -> + pcie: pcie at 9860000 { +> + pcie: pcie@9860000 { > + compatible = "hisilicon,hi3798cv200-pcie"; > + reg = <0x9860000 0x1000>, > + <0x0 0x2000>, diff --git a/a/content_digest b/N1/content_digest index 2e6f7df..7781aa5 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,8 +1,13 @@ "ref\01526004220-17030-1-git-send-email-shawn.guo@linaro.org\0" - "From\0xuwei5@hisilicon.com (Wei Xu)\0" - "Subject\0[PATCH 1/3] arm64: dts: hi3798cv200: enable PCIe support for poplar board\0" + "From\0Wei Xu <xuwei5@hisilicon.com>\0" + "Subject\0Re: [PATCH 1/3] arm64: dts: hi3798cv200: enable PCIe support for poplar board\0" "Date\0Fri, 11 May 2018 14:58:04 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Shawn Guo <shawn.guo@linaro.org>\0" + "Cc\0Jianguo Sun <sunjianguo1@huawei.com>" + Jiancheng Xue <xuejiancheng@hisilicon.com> + xuwei5@hisilicon.com + linux-arm-kernel@lists.infradead.org + " devicetree@vger.kernel.org\0" "\00:1\0" "b\0" "Hi Shawn,\n" @@ -75,7 +80,7 @@ "> \t\t\t#reset-cells = <2>;\n" "> \t\t};\n" "> \n" - "> +\t\tperictrl: peripheral-controller at 8a20000 {\n" + "> +\t\tperictrl: peripheral-controller@8a20000 {\n" "> +\t\t\tcompatible = \"hisilicon,hi3798cv200-perictrl\", \"syscon\",\n" "> +\t\t\t\t \"simple-mfd\";\n" "> +\t\t\treg = <0x8a20000 0x1000>;\n" @@ -83,7 +88,7 @@ "> +\t\t\t#size-cells = <1>;\n" "> +\t\t\tranges = <0x0 0x8a20000 0x1000>;\n" "> +\n" - "> +\t\t\tcombphy0: phy at 850 {\n" + "> +\t\t\tcombphy0: phy@850 {\n" "> +\t\t\t\tcompatible = \"hisilicon,hi3798cv200-combphy\";\n" "> +\t\t\t\treg = <0x850 0x8>;\n" "> +\t\t\t\t#phy-cells = <1>;\n" @@ -94,7 +99,7 @@ "> +\t\t\t\thisilicon,fixed-mode = <PHY_TYPE_USB3>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tcombphy1: phy at 858 {\n" + "> +\t\t\tcombphy1: phy@858 {\n" "> +\t\t\t\tcompatible = \"hisilicon,hi3798cv200-combphy\";\n" "> +\t\t\t\treg = <0x858 0x8>;\n" "> +\t\t\t\t#phy-cells = <1>;\n" @@ -106,7 +111,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> \t\tuart0: serial at 8b00000 {\n" + "> \t\tuart0: serial@8b00000 {\n" "> \t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "> \t\t\treg = <0x8b00000 0x1000>;\n" "> @@ -419,5 +452,35 @@\n" @@ -114,7 +119,7 @@ "> \t\t\tstatus = \"disabled\";\n" "> \t\t};\n" "> +\n" - "> +\t\tpcie: pcie at 9860000 {\n" + "> +\t\tpcie: pcie@9860000 {\n" "> +\t\t\tcompatible = \"hisilicon,hi3798cv200-pcie\";\n" "> +\t\t\treg = <0x9860000 0x1000>,\n" "> +\t\t\t <0x0 0x2000>,\n" @@ -147,4 +152,4 @@ "> };\n" > -b40646991e3602a2e9085d1b9d22f14cd3686626a538fa924876d0a67b404030 +6fa05c02e2a1e6265db1cefe183f9e2de229e901fce8022424758eb0ae2963ec
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