From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lu Baolu Subject: Re: [PATCH 1/1] Revert "iommu/vt-d: Clean up pasid quirk for pre-production devices" Date: Mon, 16 Jul 2018 14:02:12 +0800 Message-ID: <5B4C34E4.30004@linux.intel.com> References: <1531031001-5783-1-git-send-email-baolu.lu@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1531031001-5783-1-git-send-email-baolu.lu-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Joerg Roedel , David Woodhouse Cc: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, intel-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, ashok.raj-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, Zhenyu Wang , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: iommu@lists.linux-foundation.org SGkgSm9lcmcsCgpUaGUgZ3JhcGhpYyBndXlzIGFyZSBsb29raW5nIGZvcndhcmQgdG8gaGF2aW5n IHRoaXMgaW4gNC4xOC4KSXMgaXQgcG9zc2libGUgdG8gdGFrZSBpdCBpbiB0aGUgZm9sbG93aW5n IHJjcz8KCkJlc3QgcmVnYXJkcywKTHUgQmFvbHUKCk9uIDA3LzA4LzIwMTggMDI6MjMgUE0sIEx1 IEJhb2x1IHdyb3RlOgo+IFRoaXMgcmV2ZXJ0cyBjb21taXQgYWI5Njc0NmFhYTM0NGZiNzIwYTE5 ODI0NWE4MzdlMjY2ZmFkM2I2Mi4KPgo+IFRoZSBjb21taXQgYWI5Njc0NmFhYTM0ICgiaW9tbXUv dnQtZDogQ2xlYW4gdXAgcGFzaWQgcXVpcmsgZm9yCj4gcHJlLXByb2R1Y3Rpb24gZGV2aWNlcyIp IHRyaWdnZXJzIEVDUyBtb2RlIG9uIHNvbWUgcGxhdGZvcm1zCj4gd2hpY2ggaGF2ZSBicm9rZW4g RUNTIHN1cHBvcnQuIEFzIHRoZSByZXN1bHQsIGdyYXBoaWMgZGV2aWNlCj4gd2lsbCBiZSBpbm9w ZXJhYmxlIG9uIGJvb3QuCj4KPiBCdWd6aWxsYTogaHR0cHM6Ly9idWdzLmZyZWVkZXNrdG9wLm9y Zy9zaG93X2J1Zy5jZ2k/aWQ9MTA3MDE3Cj4KPiBDYzogQXNob2sgUmFqIDxhc2hvay5yYWpAaW50 ZWwuY29tPgo+IFNpZ25lZC1vZmYtYnk6IEx1IEJhb2x1IDxiYW9sdS5sdUBsaW51eC5pbnRlbC5j b20+Cj4gLS0tCj4gIGRyaXZlcnMvaW9tbXUvaW50ZWwtaW9tbXUuYyB8IDMyICsrKysrKysrKysr KysrKysrKysrKysrKysrKysrKy0tCj4gIGluY2x1ZGUvbGludXgvaW50ZWwtaW9tbXUuaCB8ICAx ICsKPiAgMiBmaWxlcyBjaGFuZ2VkLCAzMSBpbnNlcnRpb25zKCspLCAyIGRlbGV0aW9ucygtKQo+ Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvaW9tbXUvaW50ZWwtaW9tbXUuYyBiL2RyaXZlcnMvaW9t bXUvaW50ZWwtaW9tbXUuYwo+IGluZGV4IGIzNDRhODguLjExNWZmMjYgMTAwNjQ0Cj4gLS0tIGEv ZHJpdmVycy9pb21tdS9pbnRlbC1pb21tdS5jCj4gKysrIGIvZHJpdmVycy9pb21tdS9pbnRlbC1p b21tdS5jCj4gQEAgLTQ4NCwxNCArNDg0LDM3IEBAIHN0YXRpYyBpbnQgZG1hcl9mb3JjZWRhYzsK PiAgc3RhdGljIGludCBpbnRlbF9pb21tdV9zdHJpY3Q7Cj4gIHN0YXRpYyBpbnQgaW50ZWxfaW9t bXVfc3VwZXJwYWdlID0gMTsKPiAgc3RhdGljIGludCBpbnRlbF9pb21tdV9lY3MgPSAxOwo+ICtz dGF0aWMgaW50IGludGVsX2lvbW11X3Bhc2lkMjg7Cj4gIHN0YXRpYyBpbnQgaW9tbXVfaWRlbnRp dHlfbWFwcGluZzsKPiAgCj4gICNkZWZpbmUgSURFTlRNQVBfQUxMCQkxCj4gICNkZWZpbmUgSURF TlRNQVBfR0ZYCQkyCj4gICNkZWZpbmUgSURFTlRNQVBfQVpBTElBCQk0Cj4gIAo+IC0jZGVmaW5l IGVjc19lbmFibGVkKGlvbW11KQkoaW50ZWxfaW9tbXVfZWNzICYmIGVjYXBfZWNzKGlvbW11LT5l Y2FwKSkKPiAtI2RlZmluZSBwYXNpZF9lbmFibGVkKGlvbW11KQkoZWNzX2VuYWJsZWQoaW9tbXUp ICYmIGVjYXBfcGFzaWQoaW9tbXUtPmVjYXApKQo+ICsvKiBCcm9hZHdlbGwgYW5kIFNreWxha2Ug aGF2ZSBicm9rZW4gRUNTIHN1cHBvcnQg4oCUIG5vcm1hbCBzby1jYWxsZWQgInNlY29uZAo+ICsg KiBsZXZlbCIgdHJhbnNsYXRpb24gb2YgRE1BIHJlcXVlc3RzLXdpdGhvdXQtUEFTSUQgZG9lc24n dCBhY3R1YWxseSBoYXBwZW4KPiArICogdW5sZXNzIHlvdSBhbHNvIHNldCB0aGUgTkVTVEUgYml0 IGluIGFuIGV4dGVuZGVkIGNvbnRleHQtZW50cnkuIFdoaWNoIG9mCj4gKyAqIGNvdXJzZSBtZWFu cyB0aGF0IFNWTSBkb2Vzbid0IHdvcmsgYmVjYXVzZSBpdCdzIHRyeWluZyB0byBkbyBuZXN0ZWQK PiArICogdHJhbnNsYXRpb24gb2YgdGhlIHBoeXNpY2FsIGFkZHJlc3NlcyBpdCBmaW5kcyBpbiB0 aGUgcHJvY2VzcyBwYWdlIHRhYmxlcywKPiArICogdGhyb3VnaCB0aGUgSU9WQS0+cGh5cyBtYXBw aW5nIGZvdW5kIGluIHRoZSAic2Vjb25kIGxldmVsIiBwYWdlIHRhYmxlcy4KPiArICoKPiArICog VGhlIFZULWQgc3BlY2lmaWNhdGlvbiB3YXMgcmV0cm9hY3RpdmVseSBjaGFuZ2VkIHRvIGNoYW5n ZSB0aGUgZGVmaW5pdGlvbgo+ICsgKiBvZiB0aGUgY2FwYWJpbGl0eSBiaXRzIGFuZCBwcmV0ZW5k IHRoYXQgQnJvYWR3ZWxsL1NreWxha2UgbmV2ZXIgaGFwcGVuZWQuLi4KPiArICogYnV0IHVuZm9y dHVuYXRlbHkgdGhlIHdyb25nIGJpdCB3YXMgY2hhbmdlZC4gSXQncyBFQ1Mgd2hpY2ggaXMgYnJv a2VuLCBidXQKPiArICogZm9yIHNvbWUgcmVhc29uIGl0IHdhcyB0aGUgUEFTSUQgY2FwYWJpbGl0 eSBiaXQgd2hpY2ggd2FzIHJlZGVmaW5lZCAoZnJvbQo+ICsgKiBiaXQgMjggb24gQkRXL1NLTCB0 byBiaXQgNDAgaW4gZnV0dXJlKS4KPiArICoKPiArICogU28gb3VyIHRlc3QgZm9yIEVDUyBuZWVk cyB0byBlc2NoZXcgdGhvc2UgaW1wbGVtZW50YXRpb25zIHdoaWNoIHNldCB0aGUgb2xkCj4gKyAq IFBBU0lEIGNhcGFiaWl0eSBiaXQgMjgsIHNpbmNlIHRob3NlIGFyZSB0aGUgb25lcyBvbiB3aGlj aCBFQ1MgaXMgYnJva2VuLgo+ICsgKiBVbmxlc3Mgd2UgYXJlIHdvcmtpbmcgYXJvdW5kIHRoZSAn cGFzaWQyOCcgbGltaXRhdGlvbnMsIHRoYXQgaXMsIGJ5IHB1dHRpbmcKPiArICogdGhlIGRldmlj ZSBpbnRvIHBhc3N0aHJvdWdoIG1vZGUgZm9yIG5vcm1hbCBETUEgYW5kIHRodXMgbWFza2luZyB0 aGUgYnVnLgo+ICsgKi8KPiArI2RlZmluZSBlY3NfZW5hYmxlZChpb21tdSkgKGludGVsX2lvbW11 X2VjcyAmJiBlY2FwX2Vjcyhpb21tdS0+ZWNhcCkgJiYgXAo+ICsJCQkgICAgKGludGVsX2lvbW11 X3Bhc2lkMjggfHwgIWVjYXBfYnJva2VuX3Bhc2lkKGlvbW11LT5lY2FwKSkpCj4gKy8qIFBBU0lE IHN1cHBvcnQgaXMgdGh1cyBlbmFibGVkIGlmIEVDUyBpcyBlbmFibGVkIGFuZCAqZWl0aGVyKiBv ZiB0aGUgb2xkCj4gKyAqIG9yIG5ldyBjYXBhYmlsaXR5IGJpdHMgYXJlIHNldC4gKi8KPiArI2Rl ZmluZSBwYXNpZF9lbmFibGVkKGlvbW11KSAoZWNzX2VuYWJsZWQoaW9tbXUpICYmCQkJXAo+ICsJ CQkgICAgICAoZWNhcF9wYXNpZChpb21tdS0+ZWNhcCkgfHwgZWNhcF9icm9rZW5fcGFzaWQoaW9t bXUtPmVjYXApKSkKPiAgCj4gIGludCBpbnRlbF9pb21tdV9nZnhfbWFwcGVkOwo+ICBFWFBPUlRf U1lNQk9MX0dQTChpbnRlbF9pb21tdV9nZnhfbWFwcGVkKTsKPiBAQCAtNTU0LDYgKzU3NywxMSBA QCBzdGF0aWMgaW50IF9faW5pdCBpbnRlbF9pb21tdV9zZXR1cChjaGFyICpzdHIpCj4gIAkJCXBy aW50ayhLRVJOX0lORk8KPiAgCQkJCSJJbnRlbC1JT01NVTogZGlzYWJsZSBleHRlbmRlZCBjb250 ZXh0IHRhYmxlIHN1cHBvcnRcbiIpOwo+ICAJCQlpbnRlbF9pb21tdV9lY3MgPSAwOwo+ICsJCX0g ZWxzZSBpZiAoIXN0cm5jbXAoc3RyLCAicGFzaWQyOCIsIDcpKSB7Cj4gKwkJCXByaW50ayhLRVJO X0lORk8KPiArCQkJCSJJbnRlbC1JT01NVTogZW5hYmxlIHByZS1wcm9kdWN0aW9uIFBBU0lEIHN1 cHBvcnRcbiIpOwo+ICsJCQlpbnRlbF9pb21tdV9wYXNpZDI4ID0gMTsKPiArCQkJaW9tbXVfaWRl bnRpdHlfbWFwcGluZyB8PSBJREVOVE1BUF9HRlg7Cj4gIAkJfSBlbHNlIGlmICghc3RybmNtcChz dHIsICJ0Ym9vdF9ub2ZvcmNlIiwgMTMpKSB7Cj4gIAkJCXByaW50ayhLRVJOX0lORk8KPiAgCQkJ CSJJbnRlbC1JT01NVTogbm90IGZvcmNpbmcgb24gYWZ0ZXIgdGJvb3QuIFRoaXMgY291bGQgZXhw b3NlIHNlY3VyaXR5IHJpc2sgZm9yIHRib290XG4iKTsKPiBkaWZmIC0tZ2l0IGEvaW5jbHVkZS9s aW51eC9pbnRlbC1pb21tdS5oIGIvaW5jbHVkZS9saW51eC9pbnRlbC1pb21tdS5oCj4gaW5kZXgg MWRmOTQwMS4uZWYxNjlkNiAxMDA2NDQKPiAtLS0gYS9pbmNsdWRlL2xpbnV4L2ludGVsLWlvbW11 LmgKPiArKysgYi9pbmNsdWRlL2xpbnV4L2ludGVsLWlvbW11LmgKPiBAQCAtMTIxLDYgKzEyMSw3 IEBACj4gICNkZWZpbmUgZWNhcF9zcnMoZSkJCSgoZSA+PiAzMSkgJiAweDEpCj4gICNkZWZpbmUg ZWNhcF9lcnMoZSkJCSgoZSA+PiAzMCkgJiAweDEpCj4gICNkZWZpbmUgZWNhcF9wcnMoZSkJCSgo ZSA+PiAyOSkgJiAweDEpCj4gKyNkZWZpbmUgZWNhcF9icm9rZW5fcGFzaWQoZSkJKChlID4+IDI4 KSAmIDB4MSkKPiAgI2RlZmluZSBlY2FwX2RpcyhlKQkJKChlID4+IDI3KSAmIDB4MSkKPiAgI2Rl ZmluZSBlY2FwX25lc3QoZSkJCSgoZSA+PiAyNikgJiAweDEpCj4gICNkZWZpbmUgZWNhcF9tdHMo ZSkJCSgoZSA+PiAyNSkgJiAweDEpCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fXwppb21tdSBtYWlsaW5nIGxpc3QKaW9tbXVAbGlzdHMubGludXgtZm91bmRh dGlvbi5vcmcKaHR0cHM6Ly9saXN0cy5saW51eGZvdW5kYXRpb24ub3JnL21haWxtYW4vbGlzdGlu Zm8vaW9tbXU= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EB1BECDFAA for ; Mon, 16 Jul 2018 06:02:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4EFF820873 for ; Mon, 16 Jul 2018 06:02:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4EFF820873 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727819AbeGPG15 (ORCPT ); Mon, 16 Jul 2018 02:27:57 -0400 Received: from mga06.intel.com ([134.134.136.31]:8746 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727163AbeGPG15 (ORCPT ); Mon, 16 Jul 2018 02:27:57 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Jul 2018 23:02:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,360,1526367600"; d="scan'208";a="216294168" Received: from blu2-desk2.ccr.corp.intel.com (HELO [10.0.2.15]) ([10.239.13.1]) by orsmga004.jf.intel.com with ESMTP; 15 Jul 2018 23:02:11 -0700 Subject: Re: [PATCH 1/1] Revert "iommu/vt-d: Clean up pasid quirk for pre-production devices" To: Joerg Roedel , David Woodhouse References: <1531031001-5783-1-git-send-email-baolu.lu@linux.intel.com> Cc: ashok.raj@intel.com, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, intel-gfx@lists.freedesktop.org, Zhenyu Wang From: Lu Baolu Message-ID: <5B4C34E4.30004@linux.intel.com> Date: Mon, 16 Jul 2018 14:02:12 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <1531031001-5783-1-git-send-email-baolu.lu@linux.intel.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Joerg, The graphic guys are looking forward to having this in 4.18. Is it possible to take it in the following rcs? Best regards, Lu Baolu On 07/08/2018 02:23 PM, Lu Baolu wrote: > This reverts commit ab96746aaa344fb720a198245a837e266fad3b62. > > The commit ab96746aaa34 ("iommu/vt-d: Clean up pasid quirk for > pre-production devices") triggers ECS mode on some platforms > which have broken ECS support. As the result, graphic device > will be inoperable on boot. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107017 > > Cc: Ashok Raj > Signed-off-by: Lu Baolu > --- > drivers/iommu/intel-iommu.c | 32 ++++++++++++++++++++++++++++++-- > include/linux/intel-iommu.h | 1 + > 2 files changed, 31 insertions(+), 2 deletions(-) > > diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c > index b344a88..115ff26 100644 > --- a/drivers/iommu/intel-iommu.c > +++ b/drivers/iommu/intel-iommu.c > @@ -484,14 +484,37 @@ static int dmar_forcedac; > static int intel_iommu_strict; > static int intel_iommu_superpage = 1; > static int intel_iommu_ecs = 1; > +static int intel_iommu_pasid28; > static int iommu_identity_mapping; > > #define IDENTMAP_ALL 1 > #define IDENTMAP_GFX 2 > #define IDENTMAP_AZALIA 4 > > -#define ecs_enabled(iommu) (intel_iommu_ecs && ecap_ecs(iommu->ecap)) > -#define pasid_enabled(iommu) (ecs_enabled(iommu) && ecap_pasid(iommu->ecap)) > +/* Broadwell and Skylake have broken ECS support — normal so-called "second > + * level" translation of DMA requests-without-PASID doesn't actually happen > + * unless you also set the NESTE bit in an extended context-entry. Which of > + * course means that SVM doesn't work because it's trying to do nested > + * translation of the physical addresses it finds in the process page tables, > + * through the IOVA->phys mapping found in the "second level" page tables. > + * > + * The VT-d specification was retroactively changed to change the definition > + * of the capability bits and pretend that Broadwell/Skylake never happened... > + * but unfortunately the wrong bit was changed. It's ECS which is broken, but > + * for some reason it was the PASID capability bit which was redefined (from > + * bit 28 on BDW/SKL to bit 40 in future). > + * > + * So our test for ECS needs to eschew those implementations which set the old > + * PASID capabiity bit 28, since those are the ones on which ECS is broken. > + * Unless we are working around the 'pasid28' limitations, that is, by putting > + * the device into passthrough mode for normal DMA and thus masking the bug. > + */ > +#define ecs_enabled(iommu) (intel_iommu_ecs && ecap_ecs(iommu->ecap) && \ > + (intel_iommu_pasid28 || !ecap_broken_pasid(iommu->ecap))) > +/* PASID support is thus enabled if ECS is enabled and *either* of the old > + * or new capability bits are set. */ > +#define pasid_enabled(iommu) (ecs_enabled(iommu) && \ > + (ecap_pasid(iommu->ecap) || ecap_broken_pasid(iommu->ecap))) > > int intel_iommu_gfx_mapped; > EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped); > @@ -554,6 +577,11 @@ static int __init intel_iommu_setup(char *str) > printk(KERN_INFO > "Intel-IOMMU: disable extended context table support\n"); > intel_iommu_ecs = 0; > + } else if (!strncmp(str, "pasid28", 7)) { > + printk(KERN_INFO > + "Intel-IOMMU: enable pre-production PASID support\n"); > + intel_iommu_pasid28 = 1; > + iommu_identity_mapping |= IDENTMAP_GFX; > } else if (!strncmp(str, "tboot_noforce", 13)) { > printk(KERN_INFO > "Intel-IOMMU: not forcing on after tboot. This could expose security risk for tboot\n"); > diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h > index 1df9401..ef169d6 100644 > --- a/include/linux/intel-iommu.h > +++ b/include/linux/intel-iommu.h > @@ -121,6 +121,7 @@ > #define ecap_srs(e) ((e >> 31) & 0x1) > #define ecap_ers(e) ((e >> 30) & 0x1) > #define ecap_prs(e) ((e >> 29) & 0x1) > +#define ecap_broken_pasid(e) ((e >> 28) & 0x1) > #define ecap_dis(e) ((e >> 27) & 0x1) > #define ecap_nest(e) ((e >> 26) & 0x1) > #define ecap_mts(e) ((e >> 25) & 0x1)