Re: [cryptodev:master 124/144] drivers/crypto/hisilicon/qm.c:322:2: error: impossible constraint in 'asm'

[Zhou Wang <wangzhou1@hisilicon.com>]

On 2019/8/9 20:20, kbuild test robot wrote:
> tree:   https://kernel.googlesource.com/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git master
> head:   ec9c7d19336ee98ecba8de80128aa405c45feebb
> commit: 62c455ca853e3e352e465d66a6cc39f1f88caa60 [124/144] crypto: hisilicon - add HiSilicon ZIP accelerator support
> config: sparc64-allmodconfig (attached as .config)
> compiler: sparc64-linux-gcc (GCC) 7.4.0
> reproduce:
>         wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
>         chmod +x ~/bin/make.cross
>         git checkout 62c455ca853e3e352e465d66a6cc39f1f88caa60
>         # save the attached .config to linux build tree
>         GCC_VERSION=7.4.0 make.cross ARCH=sparc64 
> 
> If you fix the issue, kindly add following tag
> Reported-by: kbuild test robot <lkp@intel.com>
> 
> All error/warnings (new ones prefixed by >>):
> 
>    drivers/crypto/hisilicon/qm.c: In function 'qm_mb.constprop':
>>> drivers/crypto/hisilicon/qm.c:322:2: warning: asm operand 3 probably doesn't match constraints
>      asm volatile("ldp %0, %1, %3\n"
>      ^~~
>    drivers/crypto/hisilicon/qm.c:322:2: warning: asm operand 4 probably doesn't match constraints
>>> drivers/crypto/hisilicon/qm.c:322:2: error: impossible constraint in 'asm'
> --
>    drivers/crypto/hisilicon/sgl.c: In function 'hisi_acc_sg_buf_map_to_hw_sgl':
>>> drivers/crypto/hisilicon/sgl.c:181:14: warning: 'curr_sgl_dma' may be used uninitialized in this function [-Wmaybe-uninitialized]
>      *hw_sgl_dma = curr_sgl_dma;
>      ~~~~~~~~~~~~^~~~~~~~~~~~~~

Hi Herbert,

I will fix this and set dependency on arm64 for zip.

Should I just post a fix patch or repost the whole series
([PATCH v3 0/7] crypto: hisilicon: Add HiSilicon QM and ZIP controller driver) with fixes?

Best,
Zhou

> 
> vim +/asm +322 drivers/crypto/hisilicon/qm.c
> 
> 263c9959c9376e Zhou Wang 2019-08-02  315  
> 263c9959c9376e Zhou Wang 2019-08-02  316  /* 128 bit should be written to hardware at one time to trigger a mailbox */
> 263c9959c9376e Zhou Wang 2019-08-02  317  static void qm_mb_write(struct hisi_qm *qm, const void *src)
> 263c9959c9376e Zhou Wang 2019-08-02  318  {
> 263c9959c9376e Zhou Wang 2019-08-02  319  	void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE;
> 263c9959c9376e Zhou Wang 2019-08-02  320  	unsigned long tmp0 = 0, tmp1 = 0;
> 263c9959c9376e Zhou Wang 2019-08-02  321  
> 263c9959c9376e Zhou Wang 2019-08-02 @322  	asm volatile("ldp %0, %1, %3\n"
> 263c9959c9376e Zhou Wang 2019-08-02  323  		     "stp %0, %1, %2\n"
> 263c9959c9376e Zhou Wang 2019-08-02  324  		     "dsb sy\n"
> 263c9959c9376e Zhou Wang 2019-08-02  325  		     : "=&r" (tmp0),
> 263c9959c9376e Zhou Wang 2019-08-02  326  		       "=&r" (tmp1),
> 263c9959c9376e Zhou Wang 2019-08-02  327  		       "+Q" (*((char *)fun_base))
> 263c9959c9376e Zhou Wang 2019-08-02  328  		     : "Q" (*((char *)src))
> 263c9959c9376e Zhou Wang 2019-08-02  329  		     : "memory");
> 263c9959c9376e Zhou Wang 2019-08-02  330  }
> 263c9959c9376e Zhou Wang 2019-08-02  331  
> 
> :::::: The code at line 322 was first introduced by commit
> :::::: 263c9959c9376ec0217d6adc61222a53469eed3c crypto: hisilicon - add queue management driver for HiSilicon QM module
> 
> :::::: TO: Zhou Wang <wangzhou1@hisilicon.com>
> :::::: CC: Herbert Xu <herbert@gondor.apana.org.au>
> 
> ---
> 0-DAY kernel test infrastructure                Open Source Technology Center
> https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
>