Re: [PATCH 1/2 v3] dt-bindings: clock: Add X1000 bindings.

[Zhou Yanjie <zhouyanjie@zoho.com>]

Hi Paul,

On 2019年11月11日 09:13, Paul Cercueil wrote:
> Hi Zhou,
>
>
> Le dim., nov. 10, 2019 at 17:28, Zhou Yanjie <zhouyanjie@zoho.com> a 
> écrit :
>> Add the clock bindings for the X1000 Soc from Ingenic.
>>
>> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
>
> Reviewed-by: Paul Cercueil <paul@crapouillou.net>
>
>> ---
>>  .../devicetree/bindings/clock/ingenic,cgu.txt      |  1 +
>>  include/dt-bindings/clock/x1000-cgu.h              | 44 
>> ++++++++++++++++++++++
>>  2 files changed, 45 insertions(+)
>>  create mode 100644 include/dt-bindings/clock/x1000-cgu.h
>
> When you send a revised version of a patchset, it's common practice to 
> have a per-patch changelog right here. Then a cover letter is only 
> really needed for big patchsets that need extra information.
>

Thank you! I will pay attention to this next time.

>>
>> diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt 
>> b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
>> index ba5a442..75598e6 100644
>> --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
>> +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
>> @@ -11,6 +11,7 @@ Required properties:
>>    * ingenic,jz4725b-cgu
>>    * ingenic,jz4770-cgu
>>    * ingenic,jz4780-cgu
>> +  * ingenic,x1000-cgu
>>  - reg : The address & length of the CGU registers.
>>  - clocks : List of phandle & clock specifiers for clocks external to 
>> the CGU.
>>    Two such external clocks should be specified - first the external 
>> crystal
>> diff --git a/include/dt-bindings/clock/x1000-cgu.h 
>> b/include/dt-bindings/clock/x1000-cgu.h
>> new file mode 100644
>> index 00000000..bbaebaf
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/x1000-cgu.h
>> @@ -0,0 +1,44 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * This header provides clock numbers for the ingenic,x1000-cgu DT 
>> binding.
>> + *
>> + * They are roughly ordered as:
>> + *   - external clocks
>> + *   - PLLs
>> + *   - muxes/dividers in the order they appear in the x1000 
>> programmers manual
>> + *   - gates in order of their bit in the CLKGR* registers
>> + */
>> +
>> +#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__
>> +#define __DT_BINDINGS_CLOCK_X1000_CGU_H__
>> +
>> +#define X1000_CLK_EXCLK        0
>> +#define X1000_CLK_RTCLK        1
>> +#define X1000_CLK_APLL        2
>> +#define X1000_CLK_MPLL        3
>> +#define X1000_CLK_SCLKA        4
>> +#define X1000_CLK_CPUMUX    5
>> +#define X1000_CLK_CPU        6
>> +#define X1000_CLK_L2CACHE    7
>> +#define X1000_CLK_AHB0        8
>> +#define X1000_CLK_AHB2PMUX    9
>> +#define X1000_CLK_AHB2        10
>> +#define X1000_CLK_PCLK        11
>> +#define X1000_CLK_DDR        12
>> +#define X1000_CLK_MAC        13
>> +#define X1000_CLK_MSCMUX    14
>> +#define X1000_CLK_MSC0        15
>> +#define X1000_CLK_MSC1        16
>> +#define X1000_CLK_SSIPLL    17
>> +#define X1000_CLK_SSIMUX    18
>> +#define X1000_CLK_SFC        19
>> +#define X1000_CLK_I2C0        20
>> +#define X1000_CLK_I2C1        21
>> +#define X1000_CLK_I2C2        22
>> +#define X1000_CLK_UART0        23
>> +#define X1000_CLK_UART1        24
>> +#define X1000_CLK_UART2        25
>> +#define X1000_CLK_SSI        26
>> +#define X1000_CLK_PDMA        27
>> +
>> +#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */
>> -- 
>> 2.7.4
>>
>>
>
>