From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE5C0C433E3 for ; Tue, 21 Jul 2020 02:45:23 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7BBEC2065D for ; Tue, 21 Jul 2020 02:45:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="NmhbEQ64" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7BBEC2065D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=hisilicon.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=WdU9NiRsrftxAMFaJwFv2DvSTfDkDk0wHxCEGWETntY=; b=NmhbEQ64G3xS92OR/xg9/LFNn QMa2qETEaZXl9hOAqVsufwo73muuPdkShRFOqs6lP42/gwhUmHM5H5NL6fPFPp52itlBoh9vvjDsP Eb5jEuAxaVrc3+wcCTS4nG8/ikjAlly9+GbpXDSX/deJl8uFLO3FNg0pH9LAQzarzgQ7a19iDvL+D HQbZZ9VvnwvswFg598cG1s7tg/58q40d7T9cSX3aoLX21rFBJ+yarElWW4lvlO0zMfB4zBYQRDDdx fsBmjdFvbTTtLqZdOT2dQsbrSDV6+SLF/7LrEFDp9x6jr/q3Szv9qBdOucMa1dmsv4EXVIcH9ORH9 Jiu6BsQYw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jxiGI-0004T8-9E; Tue, 21 Jul 2020 02:44:10 +0000 Received: from szxga06-in.huawei.com ([45.249.212.32] helo=huawei.com) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jxiGD-0004RH-VR for linux-arm-kernel@lists.infradead.org; Tue, 21 Jul 2020 02:44:07 +0000 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 6FE68FAD4C1F2E7FF75C; Tue, 21 Jul 2020 10:44:01 +0800 (CST) Received: from [10.57.101.250] (10.57.101.250) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.487.0; Tue, 21 Jul 2020 10:43:59 +0800 Subject: Re: [PATCH] ARM: dts: hisilicon: Align L2 cache-controller nodename with dtschema To: Krzysztof Kozlowski , References: <20200626080637.4191-1-krzk@kernel.org> From: Wei Xu Message-ID: <5F16566F.1010807@hisilicon.com> Date: Tue, 21 Jul 2020 10:43:59 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 MIME-Version: 1.0 In-Reply-To: <20200626080637.4191-1-krzk@kernel.org> X-Originating-IP: [10.57.101.250] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200720_224406_763343_14EEB090 X-CRM114-Status: GOOD ( 10.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Rob Herring , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Krzysztof, On 2020/6/26 16:06, Krzysztof Kozlowski wrote: > Fix dtschema validator warnings like: > l2-cache: $nodename:0: 'l2-cache' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' > > Signed-off-by: Krzysztof Kozlowski Thanks! Applied to the hisilicon arm32 dt tree. Best Regards, Wei > --- > arch/arm/boot/dts/hi3620.dtsi | 2 +- > arch/arm/boot/dts/hisi-x5hd2.dtsi | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi > index 9c207a690df5..f0af1bf2b4d8 100644 > --- a/arch/arm/boot/dts/hi3620.dtsi > +++ b/arch/arm/boot/dts/hi3620.dtsi > @@ -71,7 +71,7 @@ > interrupt-parent = <&gic>; > ranges = <0 0xfc000000 0x2000000>; > > - L2: l2-cache { > + L2: cache-controller { > compatible = "arm,pl310-cache"; > reg = <0x100000 0x100000>; > interrupts = <0 15 4>; > diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi > index 696e6982a688..3ee7967c202d 100644 > --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi > +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi > @@ -381,7 +381,7 @@ > interrupts = <1 13 0xf01>; > }; > > - l2: l2-cache { > + l2: cache-controller { > compatible = "arm,pl310-cache"; > reg = <0x00a10000 0x100000>; > interrupts = <0 15 4>; > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.5 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EDA2C433E0 for ; Tue, 21 Jul 2020 02:44:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3CF79206E9 for ; Tue, 21 Jul 2020 02:44:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726666AbgGUCoD (ORCPT ); Mon, 20 Jul 2020 22:44:03 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:49746 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725862AbgGUCoD (ORCPT ); Mon, 20 Jul 2020 22:44:03 -0400 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 6FE68FAD4C1F2E7FF75C; Tue, 21 Jul 2020 10:44:01 +0800 (CST) Received: from [10.57.101.250] (10.57.101.250) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.487.0; Tue, 21 Jul 2020 10:43:59 +0800 Subject: Re: [PATCH] ARM: dts: hisilicon: Align L2 cache-controller nodename with dtschema To: Krzysztof Kozlowski , References: <20200626080637.4191-1-krzk@kernel.org> CC: Rob Herring , , From: Wei Xu Message-ID: <5F16566F.1010807@hisilicon.com> Date: Tue, 21 Jul 2020 10:43:59 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 MIME-Version: 1.0 In-Reply-To: <20200626080637.4191-1-krzk@kernel.org> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.57.101.250] X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Krzysztof, On 2020/6/26 16:06, Krzysztof Kozlowski wrote: > Fix dtschema validator warnings like: > l2-cache: $nodename:0: 'l2-cache' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' > > Signed-off-by: Krzysztof Kozlowski Thanks! Applied to the hisilicon arm32 dt tree. Best Regards, Wei > --- > arch/arm/boot/dts/hi3620.dtsi | 2 +- > arch/arm/boot/dts/hisi-x5hd2.dtsi | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi > index 9c207a690df5..f0af1bf2b4d8 100644 > --- a/arch/arm/boot/dts/hi3620.dtsi > +++ b/arch/arm/boot/dts/hi3620.dtsi > @@ -71,7 +71,7 @@ > interrupt-parent = <&gic>; > ranges = <0 0xfc000000 0x2000000>; > > - L2: l2-cache { > + L2: cache-controller { > compatible = "arm,pl310-cache"; > reg = <0x100000 0x100000>; > interrupts = <0 15 4>; > diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi > index 696e6982a688..3ee7967c202d 100644 > --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi > +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi > @@ -381,7 +381,7 @@ > interrupts = <1 13 0xf01>; > }; > > - l2: l2-cache { > + l2: cache-controller { > compatible = "arm,pl310-cache"; > reg = <0x00a10000 0x100000>; > interrupts = <0 15 4>; >