From: Wei Xu <xuwei5@hisilicon.com>
To: <soc@kernel.org>, "arm@kernel.org" <arm@kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Cc: Salil Mehta <salil.mehta@huawei.com>,
Tangkunshan <tangkunshan@huawei.com>,
Arnd Bergmann <arnd@arndb.de>,
Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>,
John Garry <john.garry@huawei.com>,
Linuxarm <linuxarm@huawei.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
xuwei5@hisilicon.com,
Jonathan Cameron <jonathan.cameron@huawei.com>,
Olof Johansson <olof@lixom.net>,
Shiju Jose <shiju.jose@huawei.com>,
"Liguozhu \(Kenneth\)" <liguozhu@hisilicon.com>,
Zhangyi ac <zhangyi.ac@huawei.com>,
huangdaode <huangdaode@hisilicon.com>
Subject: [GIT PULL] arm: dts: hisilicon dts updates for v5.9
Date: Tue, 21 Jul 2020 11:23:13 +0800 [thread overview]
Message-ID: <5F165FA1.2030301@hisilicon.com> (raw)
Hi ARM-SoC team,
Please consider to pull the following changes.
Thanks!
Best Regards,
Wei
---
The following changes since commit b3a9e3b9622ae10064826dccb4f7a52bd88c7407:
Linux 5.8-rc1 (2020-06-14 12:45:04 -0700)
are available in the Git repository at:
git://github.com/hisilicon/linux-hisi.git tags/hisi-arm32-dt-for-5.9
for you to fetch changes up to 5720fcdc2e5af74e51c5e3102fcefd9fb061a666:
ARM: dts: hisilicon: Align L2 cache-controller nodename with dtschema (2020-07-17 10:09:21 +0800)
----------------------------------------------------------------
ARM: DT: Hisilicon ARM32 SoCs updates for v5.9
- Update L2 cache controller nodes to fix dtschema validator warnings
for hi3620 and hix5hd2
----------------------------------------------------------------
Krzysztof Kozlowski (1):
ARM: dts: hisilicon: Align L2 cache-controller nodename with dtschema
arch/arm/boot/dts/hi3620.dtsi | 2 +-
arch/arm/boot/dts/hisi-x5hd2.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
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reply other threads:[~2020-07-21 3:24 UTC|newest]
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