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Mon, 5 Oct 2026 08:06:14 +0000 Received: from SJ0PR03MB5950.namprd03.prod.outlook.com ([fe80::53a0:bf93:6b6b:de01]) by SJ0PR03MB5950.namprd03.prod.outlook.com ([fe80::53a0:bf93:6b6b:de01%5]) with mapi id 15.21.0472.016; Mon, 5 Oct 2026 08:06:13 +0000 Message-ID: <5a6c71d7-e7a2-488e-920d-0f1bce3a8d6c@altera.com> Date: Mon, 5 Oct 2026 16:06:06 +0800 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] mmc: sdhci-cadence6: configure PHY control register per speed mode To: "Kathpalia, Tanmay" , u-boot@lists.denx.de Cc: Peng Fan , Jaehoon Chung , Tom Rini , Marek Vasut , Simon Goldschmidt , Tien Fong Chee , Ilias Apalodimas , u-boot@lists.u-boot-project.org, Chen Huei Lok , Alif Zakuan Yuslaimi , Dinesh Maniyam , Boon Khai Ng , Kok Kiang Hea References: <15e724cc7260e5f280ccced5b453b2978490df79.1787710268.git.tze.yee.ng@altera.com> <081f83da-8d7c-4cdf-8c6c-151e0372a5a1@altera.com> Content-Language: en-US From: "NG, TZE YEE" In-Reply-To: <081f83da-8d7c-4cdf-8c6c-151e0372a5a1@altera.com> Content-Type: text/plain; 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This lets each speed mode - and each board via device >>>> tree - >>>> select an appropriate value. >>>> >>>> Signed-off-by: Tze Yee Ng >>>> --- >>> >>> The PHY_CTRL default needs to be corrected. All six tables also use the >>> same 0x41F0, so this is not actually per-mode. >>> >>> Please fix the defaults. >>> >>> Regards, >>> Tanmay >> >> Hi Tanmay, >> >> 0x41F0 is the PHY_CTRL (0x2080) reset value from the PHY spec. The >> driver never wrote this register before, so the PHY already ran at >> 0x41F0 in every mode. Using it as the default in all six tables just >> preserves that (the write is a no-op unless overridden), while making >> the register tunable per mode/board via cdns,phy-ctrl- in DT, >> e.g. on Agilex5: >> >>   013b:    cdns,phy-ctrl-emmc-ddr = <0x4010>; (phony_dqs_timing = 1) >>   modular: cdns,phy-ctrl-emmc-ddr = <0x4000>; (phony_dqs_timing = 0) >> >> >> So the defaults match only because the reset value is mode-independent; >> the real tuning lives in DT. You're right that six bare 0x41F0 >> literals are misleading. For v3 I'll add a named constant >> (SDHCI_CDNS6_PHY_CTRL_REG_DEFAULT = 0x000041F0) for the default and >> reword the commit to say the register is made programmable with the >> reset value as default (no functional change), overridable per mode/ >> board via DT. >> >> Does that work for you, or did you expect distinct per-mode defaults? I >> don't have validated per-mode values, that tuning is meant to live in DT. >> >> > > I expect mode-specific, validated defaults, consistent with the other > PHY configuration values in each mode table. > Please determine the appropriate default for each speed mode rather > than using 0x41F0 universally. Board-specific DT values may still > override those defaults where required. Hi Tanmay, For v3, I'll drop the universal 0x41F0 and the per-mode cdns,phy-ctrl table entirely. The PHY_CTRL reset value already works for the SD/eMMC SDR and HS modes, so there are no per-mode defaults to validate there, the driver simply leaves PHY_CTRL untouched in those modes. Only the DDR read path is sensitive to phony_dqs_timing, so the driver programs it just for DDR50/DDR52 via a single mode-neutral property, cdns,ddr-phony-dqs-timing (shared by SD DDR50 and eMMC DDR52). It defaults to 0 (the neutral assertion timing) and a board whose DDR read path needs tuning sets it explicitly: SoCDK, eMMC and 013B use 1, while the modular SoM's longer SD path uses the default 0. The binding goes through Linux (its canonical home), currently under review: https://lore.kernel.org/all/25649477d9967bb04b12c6e60b0ee76443f356af.1790074790.git.tze.yee.ng@altera.com/ I've adopted the cdns,ddr-* naming you recommended there, so the U-Boot property matches the binding. Let me know if you see it differently. Thanks, Tze Yee