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Date: Tue, 30 Jan 2018 12:10:35 +0530
From: poza@codeaurora.org
To: Oza Pawandeep <oza.pawandeep@gmail.com>
Cc: Sinan Kaya <okaya@codeaurora.org>,
        Keith Busch <keith.busch@intel.com>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Linux PCI <linux-pci@vger.kernel.org>,
        linux-pci-owner@vger.kernel.org
Subject: Re: [PATCH 2/6] PCI/DPC: Leave interrupts enabled while handling
 event
In-Reply-To: <f0afb7badc99dcfc3b6818cc2356250d@codeaurora.org>
References: <20180129213145.26068-1-keith.busch@intel.com>
 <20180129213145.26068-2-keith.busch@intel.com>
 <56d77093-b630-148d-52ab-14dcb7714e6b@codeaurora.org>
 <CAK1A=4w-uDm+gau6WdwM=ZrgO=bWDtDKqwabxWxm2EZZb+YoKw@mail.gmail.com>
 <f0afb7badc99dcfc3b6818cc2356250d@codeaurora.org>
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On 2018-01-30 12:04, poza@codeaurora.org wrote:
> On 2018-01-30 11:59, Oza Pawandeep wrote:
>> + Oza
>> 
>> On Tue, Jan 30, 2018 at 7:41 AM, Sinan Kaya <okaya@codeaurora.org> 
>> wrote:
>>> On 1/29/2018 4:31 PM, Keith Busch wrote:
>>>> +     if (!work_busy(&dpc->work))
>>>> +             schedule_work(&dpc->work);
>>> 
>>> Isn't there a race condition between the time that dpc_work() clears 
>>> PCI_EXP_DPC_STATUS
>>> register and when work actually completes by returning from 
>>> dpc_work()?
>>> 
>>> If the interrupt arrives just in this window, this code will not 
>>> schedule the work.
>>> 
>>> --
>>> Sinan Kaya
>>> Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm 
>>> Technologies, Inc.
>>> Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a 
>>> Linux Foundation Collaborative Project.
> 
> besides, there is one more problem which I was debugging:
> if RP doesnt support MSI, then legacy interrupts are not well handled
> and we get interrupt storm.
> this is because;
> PCI_EXP_DPC_STATUS_INTERRUPT is being cleared in deferred work.
> which should get cleared in dpc_irq interrupt handler.
> I will post a patch for this, but I see there are lot of changes being
> made in dpc and aer lately.
> 
> Bjorn: Can you please help to review my AER/DPC series of patches so
> that I do not have to keep rebasing and do manual merge ?
> 
> Regards,
> Oza.

the DPC code assumes that the interrupt will be edge triggered (MSI), 
and clears interrupt in deferred work.
but for SPI (level triggered) it should be cleared in dpc_irq.

Regards,
Oza.