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([2a01:e0a:280:24f0:9db0:474c:ff43:9f5c]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47bd9936809sm35759525e9.6.2025.12.17.09.38.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 17 Dec 2025 09:38:59 -0800 (PST) Message-ID: <5b17d7e8-e4d0-4087-b104-c50a418ff24c@redhat.com> Date: Wed, 17 Dec 2025 18:38:57 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 05/33] hw/arm/smmuv3-accel: Introduce smmuv3 accel device To: Shameer Kolothum , "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" Cc: "eric.auger@redhat.com" , "peter.maydell@linaro.org" , Jason Gunthorpe , Nicolin Chen , "ddutile@redhat.com" , "berrange@redhat.com" , Nathan Chen , Matt Ochs , "smostafa@google.com" , "wangzhou1@hisilicon.com" , "jiangkunkun@huawei.com" , "jonathan.cameron@huawei.com" , "zhangfei.gao@linaro.org" , "zhenzhong.duan@intel.com" , "yi.l.liu@intel.com" , Krishnakant Jaju References: <20251120132213.56581-1-skolothumtho@nvidia.com> <20251120132213.56581-6-skolothumtho@nvidia.com> <6a062129-2b8f-420a-a4b9-87dde7574481@redhat.com> From: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= Autocrypt: addr=clg@redhat.com; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Hello Shameer, On 12/12/25 06:48, Shameer Kolothum wrote: > Hi Cédric, > >> -----Original Message----- >> From: Cédric Le Goater >> Sent: 11 December 2025 12:55 >> To: Shameer Kolothum ; qemu- >> arm@nongnu.org; qemu-devel@nongnu.org >> Cc: eric.auger@redhat.com; peter.maydell@linaro.org; Jason Gunthorpe >> ; Nicolin Chen ; >> ddutile@redhat.com; berrange@redhat.com; Nathan Chen >> ; Matt Ochs ; >> smostafa@google.com; wangzhou1@hisilicon.com; >> jiangkunkun@huawei.com; jonathan.cameron@huawei.com; >> zhangfei.gao@linaro.org; zhenzhong.duan@intel.com; yi.l.liu@intel.com; >> Krishnakant Jaju >> Subject: Re: [PATCH v6 05/33] hw/arm/smmuv3-accel: Introduce smmuv3 >> accel device >> >> External email: Use caution opening links or attachments >> >> >> On 11/20/25 14:21, Shameer Kolothum wrote: >>> Set up dedicated PCIIOMMUOps for the accel SMMUv3, since it will need >>> different callback handling in upcoming patches. This also adds a >>> CONFIG_ARM_SMMUV3_ACCEL build option so the feature can be disabled >>> at compile time. Because we now include CONFIG_DEVICES in the header to >>> check for ARM_SMMUV3_ACCEL, the meson file entry for smmuv3.c needs >> to >>> be changed to arm_ss.add. >>> >>> The “accel” property isn’t user visible yet and it will be introduced in >>> a later patch once all the supporting pieces are ready. >>> >>> Signed-off-by: Shameer Kolothum >> >>> Reviewed-by: Nicolin Chen >>> Reviewed-by: Jonathan Cameron >>> Reviewed-by: Eric Auger >>> Tested-by: Zhangfei Gao >>> Signed-off-by: Shameer Kolothum >>> --- >>> hw/arm/Kconfig | 5 ++++ >>> hw/arm/meson.build | 3 ++- >>> hw/arm/smmuv3-accel.c | 59 >> +++++++++++++++++++++++++++++++++++++++++ >>> hw/arm/smmuv3-accel.h | 27 +++++++++++++++++++ >>> hw/arm/smmuv3.c | 5 ++++ >>> include/hw/arm/smmuv3.h | 3 +++ >>> 6 files changed, 101 insertions(+), 1 deletion(-) >>> create mode 100644 hw/arm/smmuv3-accel.c >>> create mode 100644 hw/arm/smmuv3-accel.h >>> >>> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig >>> index 0cdeb60f1f..702b79a02b 100644 >>> --- a/hw/arm/Kconfig >>> +++ b/hw/arm/Kconfig >>> @@ -12,6 +12,7 @@ config ARM_VIRT >>> select ARM_GIC >>> select ACPI >>> select ARM_SMMUV3 >>> + select ARM_SMMUV3_ACCEL >>> select GPIO_KEY >>> select DEVICE_TREE >>> select FW_CFG_DMA >>> @@ -629,6 +630,10 @@ config FSL_IMX8MP_EVK >>> config ARM_SMMUV3 >>> bool >>> >>> +config ARM_SMMUV3_ACCEL >>> + bool >>> + depends on ARM_SMMUV3 && IOMMUFD >>> + >>> config FSL_IMX6UL >>> bool >>> default y >>> diff --git a/hw/arm/meson.build b/hw/arm/meson.build >>> index aeaf654790..c250487e64 100644 >>> --- a/hw/arm/meson.build >>> +++ b/hw/arm/meson.build >>> @@ -84,7 +84,8 @@ arm_common_ss.add(when: 'CONFIG_ARMSSE', >> if_true: files('armsse.c')) >>> arm_common_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', >> 'mcimx7d-sabre.c')) >>> arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP', if_true: files('fsl- >> imx8mp.c')) >>> arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true: >> files('imx8mp-evk.c')) >>> -arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: >> files('smmuv3.c')) >>> +arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) >>> +arm_ss.add(when: 'CONFIG_ARM_SMMUV3_ACCEL', if_true: >> files('smmuv3-accel.c')) >>> arm_common_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl- >> imx6ul.c', 'mcimx6ul-evk.c')) >>> arm_common_ss.add(when: 'CONFIG_NRF51_SOC', if_true: >> files('nrf51_soc.c')) >>> arm_common_ss.add(when: 'CONFIG_XEN', if_true: files( >>> diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c >>> new file mode 100644 >>> index 0000000000..99ef0db8c4 >>> --- /dev/null >>> +++ b/hw/arm/smmuv3-accel.c >>> @@ -0,0 +1,59 @@ >>> +/* >>> + * Copyright (c) 2025 Huawei Technologies R & D (UK) Ltd >>> + * Copyright (C) 2025 NVIDIA >>> + * Written by Nicolin Chen, Shameer Kolothum >>> + * >>> + * SPDX-License-Identifier: GPL-2.0-or-later >>> + */ >>> + >>> +#include "qemu/osdep.h" >>> + >>> +#include "hw/arm/smmuv3.h" >>> +#include "smmuv3-accel.h" >>> + >>> +static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *bs, >> SMMUPciBus *sbus, >>> + PCIBus *bus, int devfn) >>> +{ >>> + SMMUDevice *sdev = sbus->pbdev[devfn]; >>> + SMMUv3AccelDevice *accel_dev; >>> + >>> + if (sdev) { >>> + return container_of(sdev, SMMUv3AccelDevice, sdev); >>> + } >>> + >>> + accel_dev = g_new0(SMMUv3AccelDevice, 1); >> >> oh. This is not a QOM object :/ > > Right. > >> >>> + sdev = &accel_dev->sdev; >>> + >>> + sbus->pbdev[devfn] = sdev; >>> + smmu_init_sdev(bs, sdev, bus, devfn); >>> + return accel_dev; >>> +} >>> + >>> +/* >>> + * Find or add an address space for the given PCI device. >>> + * >>> + * If a device matching @bus and @devfn already exists, return its >>> + * corresponding address space. Otherwise, create a new device entry >>> + * and initialize address space for it. >>> + */ >>> +static AddressSpace *smmuv3_accel_find_add_as(PCIBus *bus, void >> *opaque, >>> + int devfn) >>> +{ >>> + SMMUState *bs = opaque; >>> + SMMUPciBus *sbus = smmu_get_sbus(bs, bus); >>> + SMMUv3AccelDevice *accel_dev = smmuv3_accel_get_dev(bs, sbus, >> bus, devfn); >>> + SMMUDevice *sdev = &accel_dev->sdev; >>> + >>> + return &sdev->as; >>> +} >>> + >>> +static const PCIIOMMUOps smmuv3_accel_ops = { >>> + .get_address_space = smmuv3_accel_find_add_as, >>> +}; >>> + >>> +void smmuv3_accel_init(SMMUv3State *s) >>> +{ >>> + SMMUState *bs = ARM_SMMU(s); >>> + >>> + bs->iommu_ops = &smmuv3_accel_ops; >> >> again, I think this should be a sSMMUv3Class attribute. > > See below. >> >>> +} >>> diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h >>> new file mode 100644 >>> index 0000000000..0dc6b00d35 >>> --- /dev/null >>> +++ b/hw/arm/smmuv3-accel.h >>> @@ -0,0 +1,27 @@ >>> +/* >>> + * Copyright (c) 2025 Huawei Technologies R & D (UK) Ltd >>> + * Copyright (C) 2025 NVIDIA >>> + * Written by Nicolin Chen, Shameer Kolothum >>> + * >>> + * SPDX-License-Identifier: GPL-2.0-or-later >>> + */ >>> + >>> +#ifndef HW_ARM_SMMUV3_ACCEL_H >>> +#define HW_ARM_SMMUV3_ACCEL_H >>> + >>> +#include "hw/arm/smmu-common.h" >>> +#include CONFIG_DEVICES >>> + >>> +typedef struct SMMUv3AccelDevice { >>> + SMMUDevice sdev; >>> +} SMMUv3AccelDevice; >>> + >>> +#ifdef CONFIG_ARM_SMMUV3_ACCEL >>> +void smmuv3_accel_init(SMMUv3State *s); >>> +#else >>> +static inline void smmuv3_accel_init(SMMUv3State *s) >>> +{ >>> +} >>> +#endif >>> + >>> +#endif /* HW_ARM_SMMUV3_ACCEL_H */ >>> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c >>> index bcf8af8dc7..ef991cb7d8 100644 >>> --- a/hw/arm/smmuv3.c >>> +++ b/hw/arm/smmuv3.c >>> @@ -32,6 +32,7 @@ >>> #include "qapi/error.h" >>> >>> #include "hw/arm/smmuv3.h" >>> +#include "smmuv3-accel.h" >>> #include "smmuv3-internal.h" >>> #include "smmu-internal.h" >>> >>> @@ -1882,6 +1883,10 @@ static void smmu_realize(DeviceState *d, Error >> **errp) >>> SysBusDevice *dev = SYS_BUS_DEVICE(d); >>> Error *local_err = NULL; >>> >>> + if (s->accel) { >>> + smmuv3_accel_init(s); >>> + } >>> + >>> c->parent_realize(d, &local_err); >>> if (local_err) { >>> error_propagate(errp, local_err); >>> diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h >>> index d183a62766..bb7076286b 100644 >>> --- a/include/hw/arm/smmuv3.h >>> +++ b/include/hw/arm/smmuv3.h >>> @@ -63,6 +63,9 @@ struct SMMUv3State { >>> qemu_irq irq[4]; >>> QemuMutex mutex; >>> char *stage; >>> + >>> + /* SMMU has HW accelerator support for nested S1 + s2 */ >>> + bool accel; >> >> Have you considered modeling with a QOM object instead ? > > A bit of history on this: > > The SMMUv3 accel support was introduced first as a separate device, > -device arm-smmuv3-accel > > https://lore.kernel.org/qemu-devel/20250311141045.66620-4-shameerali.kolothum.thodi@huawei.com/ > > However, the general consensus at that time was that we should instead > model it on the -device arm-smmuv3 itself, with an added "accel" property. > > Eric had also suggested making use of something similar to the > TYPE_VFIO_IOMMU_IOMMUFD / LEGACY classes for selecting the iommu_ops. > https://lore.kernel.org/qemu-devel/1105d100-dd1e-4aca-b518-50f903967416@redhat.com/ > > In RFCv3, I did introduce a TYPE_ARM_SMMUV3_ACCEL object class, but we > later found that it wasn’t doing much beyond helping to retrieve the iommu_ops > based on the object type, so decided to drop it. > https://lore.kernel.org/qemu-devel/71ca9132-8deb-4f57-abb0-2bcc0fe93ae9@redhat.com/ > > From your feedback, I understand that you would like to revisit that approach > again. Just to make sure I get this right, is the SMMUv3AccelClass you have in > mind meant to be an abstract object, like HOST_IOMMU_DEVICE, or are > you suggesting another child device object? HOST_IOMMU_DEVICE are for host IOMMU backends (VFIO IOMMU Type1 legacy and IOMMUFD). I was imagining an "arm-smmuv3" children class for acceleration. I understand I am jumping a bit late in the discussion. Sorry about that and the late reply also. I have been experimenting with your series on other systems and on an ARM system with MLX5 VFs and an L4 GPU. I had to fake CANWBS support in the host kernel to make progress. On a side note, I also pulled in a patch from Nicolin to add dmabuf support and it seemed to behave ok. This would require more in-depth P2P testing. That's another topic we should discuss in the QEMU 11.0 cycle. > Please let me know if there is an example/precedent, I can look at for a similar > object model in QEMU. Now regarding modeling, it is more or less a design choice. But while I scanned through the code, I felt there was some problems that could be solved in a cleaner way with a sub class. The changes are mostly about moving code in different places and changing/removing the "if (s->accel) parts". Don't change everything now, I will check RFCv3. Nevertheless, they are several more issues, build breakages and also runtime breakage that should be addressed. Let's do that first. Furthermore, an (idealistic) design principle of QEMU that we tend to forget is to offer acceleration when possible and else fallback to emulation, in order to guarantee parity of features between different hardware. I expected the "arm-smmuv3" device to decide to operate in accelerated mode when ever possible, i.e when the IOMMUFD backend (the SMMUV3 + the FW) offers the right level of functionality. This would allow the machine to maintain a constant view of the sMMUv3 device and facilitate its integration with management layers and ease migration too. I understand this is complex, it has been done for some interrupt controllers, and this is not the approach of the series. That said, what about integration with libvirt ? Thanks, C.