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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4390d966faasm49362345e9.23.2025.02.06.01.24.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 06 Feb 2025 01:24:28 -0800 (PST) Message-ID: <5b1a3d9a-e898-4dca-bc7a-9a182556b519@linaro.org> Date: Thu, 6 Feb 2025 10:24:27 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 13/17] hw/misc: Support NPCM8XX CLK Module Registers To: Hao Wu , peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, venture@google.com, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, hskinnemoen@google.com, titusr@google.com, chli30@nuvoton.corp-partner.google.com References: <20250206013105.3228344-1-wuhaotsh@google.com> <20250206013105.3228344-14-wuhaotsh@google.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250206013105.3228344-14-wuhaotsh@google.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: zb8Rexqa02pL On 6/2/25 02:31, Hao Wu wrote: > NPCM8XX adds a few new registers and have a different set of reset > values to the CLK modules. This patch supports them. > > This patch doesn't support the new clock values generated by these > registers. Currently no modules use these new clock values so they > are not necessary at this point. > Implementation of these clocks might be required when implementing > these modules. > > Reviewed-by: Titus Rwantare > Reviewed-by: Peter Maydell > Signed-off-by: Hao Wu > --- > hw/misc/npcm_clk.c | 113 ++++++++++++++++++++++++++++++++++++- > include/hw/misc/npcm_clk.h | 10 +++- > 2 files changed, 120 insertions(+), 3 deletions(-) > +enum NPCM8xxCLKRegisters { > + NPCM8XX_CLK_CLKEN1, > + NPCM8XX_CLK_CLKSEL, > + NPCM8XX_CLK_CLKDIV1, > + NPCM8XX_CLK_PLLCON0, > + NPCM8XX_CLK_PLLCON1, > + NPCM8XX_CLK_SWRSTR, > + NPCM8XX_CLK_IPSRST1 = 0x20 / sizeof(uint32_t), > + NPCM8XX_CLK_IPSRST2, > + NPCM8XX_CLK_CLKEN2, > + NPCM8XX_CLK_CLKDIV2, > + NPCM8XX_CLK_CLKEN3, > + NPCM8XX_CLK_IPSRST3, > + NPCM8XX_CLK_WD0RCR, > + NPCM8XX_CLK_WD1RCR, > + NPCM8XX_CLK_WD2RCR, > + NPCM8XX_CLK_SWRSTC1, > + NPCM8XX_CLK_SWRSTC2, > + NPCM8XX_CLK_SWRSTC3, > + NPCM8XX_CLK_TIPRSTC, > + NPCM8XX_CLK_PLLCON2, > + NPCM8XX_CLK_CLKDIV3, > + NPCM8XX_CLK_CORSTC, > + NPCM8XX_CLK_PLLCONG, > + NPCM8XX_CLK_AHBCKFI, > + NPCM8XX_CLK_SECCNT, > + NPCM8XX_CLK_CNTR25M, > + /* Registers unique to NPCM8XX SoC */ > + NPCM8XX_CLK_CLKEN4, > + NPCM8XX_CLK_IPSRST4, > + NPCM8XX_CLK_BUSTO, > + NPCM8XX_CLK_CLKDIV4, > + NPCM8XX_CLK_WD0RCRB, > + NPCM8XX_CLK_WD1RCRB, > + NPCM8XX_CLK_WD2RCRB, > + NPCM8XX_CLK_SWRSTC1B, > + NPCM8XX_CLK_SWRSTC2B, > + NPCM8XX_CLK_SWRSTC3B, > + NPCM8XX_CLK_TIPRSTCB, > + NPCM8XX_CLK_CORSTCB, > + NPCM8XX_CLK_IPSRSTDIS1, > + NPCM8XX_CLK_IPSRSTDIS2, > + NPCM8XX_CLK_IPSRSTDIS3, > + NPCM8XX_CLK_IPSRSTDIS4, > + NPCM8XX_CLK_CLKENDIS1, > + NPCM8XX_CLK_CLKENDIS2, > + NPCM8XX_CLK_CLKENDIS3, > + NPCM8XX_CLK_CLKENDIS4, > + NPCM8XX_CLK_THRTL_CNT, > + NPCM8XX_CLK_REGS_END, I suppose by '_END' you mean '_COUNT'. Better define unrelated to the enum, to avoid confusing static analyzers: #define NPCM8XX_CLK_REGS_COUNT (NPCM8XX_CLK_THRTL_CNT + 1) > +};