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Mon, 21 Sep 2026 06:52:25 -0700 (PDT) Received: from [192.168.29.146] ([49.43.232.81]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-144d55f299fsm36081162c88.15.2026.09.21.06.52.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 21 Sep 2026 06:52:24 -0700 (PDT) Message-ID: <5c16f588-3ea4-4f37-baca-e5a2807592de@oss.qualcomm.com> Date: Mon, 21 Sep 2026 19:22:16 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 0/5] PCI: qcom: Add PCIe support for Shikra SoC To: Konrad Dybcio , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Andersson , Chaitanya Chundru , Bartosz Golaszewski , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org References: <20260831-shikra-upstream-v2-0-406661d75afa@oss.qualcomm.com> Content-Language: en-US From: Sushrut Shree Trivedi In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIxMDIwMSBTYWx0ZWRfXwxghfIoweiWs gCLXcTXwXSvK12MOAONi6/kryajSy3iWTL68YVAvV3HR8cCe+R5cp5SSD6fsZyOxWOwsmMaru5w WT2erMEw/oy9Vlk/TTQ96gQHts9mQhE= X-Authority-Analysis: v=2.4 cv=AsR7T+9P c=1 sm=1 tr=0 ts=6ab1369a cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=gjxls31er4aXgMEaaoPcOA==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=xfGM6EskjLEd39232uAA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-GUID: lgOSNEo4VfEEIuxP5DuzwgIB1Qwavj3D X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIxMDIwMSBTYWx0ZWRfX9KlbL9Ll+5ti KvK5XRHHHh8MyJJZKXr2ZAYQhH9Eunq/MbgSOrJZLbTaiyCOyuwwdazMuOhFFYYmk3xLIfvlR8M tgrKbqx41fGIHWC+hbaKr3k5KDyyX1/FPGDH3FKb3h8SFr0YpAab1VKBxUdurHEg7nevUBhem0X dh7OcYkZetoO0nd3AjBTLUsCwZUzdFU339ppDKI75FGed9dfqYAjGL9FVNOD5HktkbaeZPhHc/o ogm5VfDWayK9FP3NS/XBSSps24HK4z8gXZNZMC2d/krgKYSx4CF+qv8klsFDeJjtroFf/+e1PHU pZiU9YIIQd9+qT8CD2jywY+pdj03IRFswtv9KrximK4gmwps9R3jSfL1rdv9aSZBkXHqLQfkwJ0 /UXlXtcA15RVT2fvIHIux1BespghdeVNR7d3DffkGTh+PWxkS6XCHHSV9bHebnvTNASy16iQBEh 7wXVmEvmDceuHbbNuyQ== X-Proofpoint-ORIG-GUID: lgOSNEo4VfEEIuxP5DuzwgIB1Qwavj3D X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-21_04,2026-09-21_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 malwarescore=0 suspectscore=0 clxscore=1015 impostorscore=0 adultscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609210201 On 9/2/2026 2:16 PM, Konrad Dybcio wrote: > On 8/31/26 9:26 AM, Sushrut Shree Trivedi wrote: >> Add PCIe support for Shikra target, by adding dt-bindings for phy, >> controller and corresponding phy & controller drivers/device-tree >> changes. >> >> Shikra RC is connected to TC9563 PCIe switch on all three >> EVK variants: CQS, CQM and IQS. The individual downstream ports >> of TC9563 connect like below: >> >> DSP1: M.2 B-Key for 5G Modem >> DSP2: M.2 M-Key for NVMe >> DSP3: Embedded ethernet device >> >> Power and reset to M.2 B and M.2 M slot are controlled via >> TC9563 GPIO's. Since TC9563 GPIO driver from Alex is still >> under active review, current series only contains basic PCIe >> enablement for the controller / PHY. TC9563 enablement changes >> would be posted as a separate series once the GPIO driver is >> ready. >> >> [1] https://lore.kernel.org/all/e2inl7k5gsjj6oomv2k5ximuzpb3gfiz66ufet3b4hvov7zqt4@qz4pifbos7yf/ >> >> Signed-off-by: Sushrut Shree Trivedi >> --- >> Changes in v2: >> - Remove TC9563 specific changes [Mani] >> - Fix commit descriptions/subjects [Bjorn Helgaas] >> - Fix PCIe controller dt-binding errors [Krzysztof Kozlowski / Mani] >> - Document PCIe Gen2 limitation in controller node & commit msg [Konrad Dybcio / Mani] >> - Add GCC_PCIE_SLEEP_CLK (which is actually PHY AUX CLK) in PCIe PHY >> node. > You also silently adjusted the OPP levels in the DT patch: My bad;  I did ACK Mani's comment in v1 regarding higher voltage corner votes. Will mention in cover letter next time onwards. > > < + required-opps = <&rpmpd_opp_nom>; > --- >> + required-opps = <&rpmpd_opp_low_svs>; > > is the lower one suitable? Yes, Gen2 can be supported with low svs corner as per HW team. > > Konrad