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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49cd775dae8sm83661815e9.9.2026.08.30.22.23.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 30 Aug 2026 22:23:39 -0700 (PDT) Message-ID: <5d280603-e2f9-4d24-a31b-19f908a30c55@redhat.com> Date: Mon, 31 Aug 2026 07:23:38 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC v5 21/28] hw/arm/smmuv3: Implement SMMU_S_INIT register Content-Language: en-US To: Tao Tang , Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Mostafa Saleh , Chao Liu , Jim MacArthur References: <20260813161515.2788900-1-tangtao1634@phytium.com.cn> <20260813162624.2809349-1-tangtao1634@phytium.com.cn> From: Eric Auger In-Reply-To: <20260813162624.2809349-1-tangtao1634@phytium.com.cn> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Tao, On 8/13/26 6:26 PM, Tao Tang wrote: > Implement read/write handlers for the SMMU_S_INIT secure-only register. > > Writing INV_ALL provides a mechanism for software to perform a global > invalidation of ALL caches within the SMMU, including IOTLBs and > configuration caches across all security states. > > The MMIO dispatcher decodes the target register bank from the offset and > normalizes Secure-window offsets by subtracting SMMU_SECURE_REG_START > before switching on the bank-local offset. S_INIT is a Secure-only > register and its A_S_INIT constant is an absolute Secure-window offset, > so the handler matches it using A_S_INIT - SMMU_SECURE_REG_START and > rejects accesses through Non-secure banks. > > Signed-off-by: Tao Tang > Reviewed-by: Pierrick Bouvier > --- > hw/arm/smmuv3.c | 43 +++++++++++++++++++++++++++++++++++++++++++ > hw/arm/trace-events | 1 + > 2 files changed, 44 insertions(+) > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index d69fc0898af..dc3fa618883 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -393,6 +393,21 @@ static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf, > > } > > +static void smmuv3_invalidate_all_caches(SMMUv3State *s) > +{ > + SMMUState *bs = &s->smmu_state; > + trace_smmuv3_invalidate_all_caches(); > + > + /* Clear all cached configs including STE and CD */ > + if (bs->configs) { > + g_hash_table_remove_all(bs->configs); > + } > + > + /* Invalidate all SMMU IOTLB entries */ > + smmu_inv_notifiers_all(&s->smmu_state); > + smmu_iotlb_inv_all(bs); > +} > + > static SMMUTranslationStatus smmuv3_do_translate(SMMUv3State *s, hwaddr addr, > SMMUTransCfg *cfg, > SMMUEventInfo *event, > @@ -2206,7 +2221,29 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset, > > bank->eventq_irq_cfg2 = data; > break; > + case A_S_INIT - SMMU_SECURE_REG_START: > + if (reg_sec_sid != SMMU_SEC_SID_S) { > + goto unhandled; > + } > + if (data & R_S_INIT_INV_ALL_MASK) { > + /* > + * If SMMU_ROOT_CR0.GPCEN == 0, a write of 1 to INV_ALL when any > + * SMMU_(*_)CR0.SMMUEN == 1, .... , is CONSTRAINED UNPREDICTABLE > + * according to (IHI 0070G.b) 6.3.62 SMMU_S_INIT, Page 465. > + */ > + if (!smmuv3_smmu_disabled_stable(s, SMMU_SEC_SID_NS) || > + !smmuv3_smmu_disabled_stable(s, SMMU_SEC_SID_S)) { > + /* CONSTRAINED UNPREDICTABLE behavior: Ignore this write */ > + qemu_log_mask(LOG_GUEST_ERROR, "S_INIT write ignored: " > + "(S_)CR0.SMMUEN or (S_)CR0ACK.SMMUEN is set\n"); > + return MEMTX_OK; > + } shall we really bother: I read: " If SMMU_ROOT_CR0.GPCEN == 0, a write of 1 to INV_ALL when any SMMU_(*_)CR0.SMMUEN == 1, or an Update of any SMMUEN to 1 is in progress, or SMMU_ROOT_CR0.ACCESSEN == 1, or an Update of ACCESSEN to 1 is in progress, is CONSTRAINED UNPREDICTABLE and has one of the following behaviors: • The write is IGNORED. • The invalidation operation occurs and completes, with INV_ALL reset to 0 on completion. " So the second behavior would let us simplify the code, no? By the way where is GPCEN checked? Eric > + smmuv3_invalidate_all_caches(s); > + } > + /* Synchronous emulation: invalidation completed instantly. */ > + break; > default: > + unhandled: > qemu_log_mask(LOG_UNIMP, > "%s Unexpected 32-bit access to 0x%"PRIx64" (WI)\n", > __func__, offset); > @@ -2444,6 +2481,12 @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset, > > *data = bank->eventq_irq_cfg2; > return MEMTX_OK; > + case A_S_INIT - SMMU_SECURE_REG_START: > + if (reg_sec_sid != SMMU_SEC_SID_S) { > + goto unhandled; > + } > + *data = 0; > + return MEMTX_OK; > default: > unhandled: > *data = 0; > diff --git a/hw/arm/trace-events b/hw/arm/trace-events > index 7cd4eb38578..ac9f737a5e6 100644 > --- a/hw/arm/trace-events > +++ b/hw/arm/trace-events > @@ -67,6 +67,7 @@ smmuv3_cmdq_tlbi_s12_vmid(int vmid) "vmid=%d" > smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s" > smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s" > smmuv3_inv_notifiers_iova(const char *name, int asid, int vmid, uint64_t iova, uint8_t tg, uint64_t num_pages, int stage) "iommu mr=%s asid=%d vmid=%d iova=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" stage=%d" > +smmuv3_invalidate_all_caches(void) "Invalidate all SMMU caches and TLBs" > smmu_reset_exit(void) "" > > #smmuv3-accel.c