tegra/for-next boot bisection: v5.4-rc1-43-g564c032098ad on tegra124-nyan-big

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tegra/for-next boot bisection: v5.4-rc1-43-g564c032098ad on tegra124-nyan-big

Summary:
  Start:      564c032098ad Merge branch for-5.5/clk into for-next
  Details:    https://kernelci.org/boot/id/5db73d0459b514ce1360ee73
  Plain log:  https://storage.kernelci.org//tegra/for-next/v5.4-rc1-43-g564c032098ad/arm/multi_v7_defconfig+CONFIG_SMP=n/gcc-8/lab-collabora/boot-tegra124-nyan-big.txt
  HTML log:   https://storage.kernelci.org//tegra/for-next/v5.4-rc1-43-g564c032098ad/arm/multi_v7_defconfig+CONFIG_SMP=n/gcc-8/lab-collabora/boot-tegra124-nyan-big.html
  Result:     03fcfdabb05e clk: tegra: Reimplement SOR clock on Tegra124

Checks:
  revert:     PASS
  verify:     PASS

Parameters:
  Tree:       tegra
  URL:        https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git
  Branch:     for-next
  Target:     tegra124-nyan-big
  CPU arch:   arm
  Lab:        lab-collabora
  Compiler:   gcc-8
  Config:     multi_v7_defconfig+CONFIG_SMP=n
  Test suite: boot

Breaking commit found:

-------------------------------------------------------------------------------
commit 03fcfdabb05ea8d63f571649c4f8fc6840750c69
Author: Thierry Reding <treding@nvidia.com>
Date:   Thu Jul 25 18:19:00 2019 +0200

    clk: tegra: Reimplement SOR clock on Tegra124
    
    In order to allow the display driver to deal uniformly with all SOR
    generations, implement the SOR clocks in a way that is compatible with
    Tegra186 and later.
    
    Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 7d231529c3a5..b3110d5b5a6c 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1005,20 +1005,24 @@ static struct tegra_devclk devclks[] __initdata = {
 	{ .con_id = "hda2hdmi", .dt_id = TEGRA124_CLK_HDA2HDMI },
 };
 
-static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
-	"pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c",
-	"pll_d2_out0", "clk_m"
+static const char * const sor0_parents[] = {
+	"pll_p_out0", "pll_m_out0", "pll_d_out0", "pll_a_out0", "pll_c_out0",
+	"pll_d2_out0", "clk_m",
 };
-#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
 
-static const char *mux_clkm_plldp_sor0out[] = {
-	"clk_m", "pll_dp", "sor0_out",
+static const char * const sor0_out_parents[] = {
+	"clk_m", "sor0_pad_clkout",
 };
-#define mux_clkm_plldp_sor0out_idx NULL
 
 static struct tegra_periph_init_data tegra124_periph[] = {
-	MUX8_NOGATE_LOCK("sor0_out", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_SOR0, tegra_clk_sor0_out, &sor0_lock),
-	NODIV("sor0", mux_clkm_plldp_sor0out, CLK_SOURCE_SOR0, 14, 3, 182, 0, tegra_clk_sor0, &sor0_lock),
+	TEGRA_INIT_DATA_TABLE("sor0", NULL, NULL, sor0_parents,
+			      CLK_SOURCE_SOR0, 29, 0x7, 0, 0, 0, 0,
+			      0, 182, 0, tegra_clk_sor0, NULL, 0,
+			      &sor0_lock),
+	TEGRA_INIT_DATA_TABLE("sor0_out", NULL, NULL, sor0_out_parents,
+			      CLK_SOURCE_SOR0, 14, 0x1, 0, 0, 0, 0,
+			      0, 0, TEGRA_PERIPH_NO_GATE, tegra_clk_sor0_out,
+			      NULL, 0, &sor0_lock),
 };
 
 static struct clk **clks;
-------------------------------------------------------------------------------


Git bisection log:

-------------------------------------------------------------------------------
git bisect start
# good: [54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c] Linux 5.4-rc1
git bisect good 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c
# bad: [564c032098ad56372b69ad19d9c92167d8e0e0f4] Merge branch for-5.5/clk into for-next
git bisect bad 564c032098ad56372b69ad19d9c92167d8e0e0f4
# good: [23939968c9d885c4b467f49b84deadf96bd3cadf] arm64: tegra: Enable DisplayPort on Jetson AGX Xavier
git bisect good 23939968c9d885c4b467f49b84deadf96bd3cadf
# good: [811ec063dc042065bc0fad83c374202c436f660f] Merge branch for-5.5/soc into for-next
git bisect good 811ec063dc042065bc0fad83c374202c436f660f
# bad: [c7dd92281a822e3d1072cd6c0a2e5d4e90cf1e38] clk: tegra: Reimplement SOR clocks on Tegra210
git bisect bad c7dd92281a822e3d1072cd6c0a2e5d4e90cf1e38
# good: [bbcaaf40ed81b4f9326f57dddd4b4a86dc763493] clk: tegra: Move SOR0 implementation to Tegra124
git bisect good bbcaaf40ed81b4f9326f57dddd4b4a86dc763493
# bad: [03fcfdabb05ea8d63f571649c4f8fc6840750c69] clk: tegra: Reimplement SOR clock on Tegra124
git bisect bad 03fcfdabb05ea8d63f571649c4f8fc6840750c69
# good: [b761e39ee45cd51f2f0d506ee998c1d9cc03d8cd] clk: tegra: Rename sor0_lvds to sor0_out
git bisect good b761e39ee45cd51f2f0d506ee998c1d9cc03d8cd
# first bad commit: [03fcfdabb05ea8d63f571649c4f8fc6840750c69] clk: tegra: Reimplement SOR clock on Tegra124
-------------------------------------------------------------------------------