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From: "Das, Nirmoy" <nirmoy.das@intel.com>
To: <priyanka.dandamudi@intel.com>, <matthew.auld@intel.com>,
	<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH v4 2/2] drm/i915: Add lmem_bar_size modparam
Date: Mon, 11 Jul 2022 16:03:03 +0200	[thread overview]
Message-ID: <5f563adb-8eca-c5b6-fe3a-e4adeb8ff610@intel.com> (raw)
In-Reply-To: <20220710172925.2465158-3-priyanka.dandamudi@intel.com>

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On 7/10/2022 7:29 PM, priyanka.dandamudi@intel.com wrote:
> From: Priyanka Dandamudi<priyanka.dandamudi@intel.com>
>
> For testing purposes, support forcing the lmem_bar_size through a new
> modparam. In CI we only have a limited number of configurations for DG2,
> but we still need to be reasonably sure we get a usable device (also
> verifying we report the correct values for things like
> probed_cpu_visible_size etc) with all the potential lmem_bar sizes that
> we might expect see in the wild.
>
> v2: Update commit message and a minor modification.(Matt)
>
> v3: Optimised lmem bar size code and modified code to resize
> bar maximum upto lmem_size instead of maximum supported size.(Nirmoy)
>
> v4: Optimised lmem bar size code.(Nirmoy)
>
> Cc: Matthew Auld<matthew.auld@intel.com>
> Cc: Nirmoy Das<nirmoy.das@intel.com>
>
> Signed-off-by: Priyanka Dandamudi<priyanka.dandamudi@intel.com>

|Reviewed-by: Nirmoy Das<nirmoy.das@intel.com> |

> ---
>   drivers/gpu/drm/i915/gt/intel_region_lmem.c | 33 +++++++++++++++++----
>   drivers/gpu/drm/i915/i915_params.c          |  2 ++
>   drivers/gpu/drm/i915/i915_params.h          |  1 +
>   3 files changed, 31 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> index 129e5d8b080d..22dbf986217c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> @@ -51,15 +51,38 @@ static void i915_resize_lmem_bar(struct drm_i915_private *i915, resource_size_t
>   	struct pci_bus *root = pdev->bus;
>   	struct resource *root_res;
>   	resource_size_t rebar_size;
> +	resource_size_t current_size;
>   	u32 pci_cmd;
>   	int i;
>   
> -	rebar_size = roundup_pow_of_two(pci_resource_len(pdev, LMEM_BAR_NUM));
> +	current_size = roundup_pow_of_two(pci_resource_len(pdev, LMEM_BAR_NUM));
>   
> -	if (rebar_size != roundup_pow_of_two(lmem_size))
> -		rebar_size = lmem_size;
> -	else
> -		return;
> +	if (i915->params.lmem_bar_size) {
> +		u32 bar_sizes;
> +
> +		rebar_size = i915->params.lmem_bar_size *
> +			(resource_size_t)SZ_1M;
> +		bar_sizes = pci_rebar_get_possible_sizes(pdev,
> +							 LMEM_BAR_NUM);
> +
> +		if (rebar_size == current_size)
> +			return;
> +
> +		if (!(bar_sizes & BIT(pci_rebar_bytes_to_size(rebar_size))) ||
> +		    rebar_size >= roundup_pow_of_two(lmem_size)) {
> +				rebar_size = lmem_size;
> +
> +				drm_info(&i915->drm, "Given bar size is not within supported size,"
> +						     "setting it to default: %llu\n", lmem_size);
> +		}
> +	} else {
> +		rebar_size = current_size;
> +
> +		if (rebar_size != roundup_pow_of_two(lmem_size))
> +			rebar_size = lmem_size;
> +		else
> +			return;
> +	}
>   
>   	/* Find out if root bus contains 64bit memory addressing */
>   	while (root->parent)
> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
> index 701fbc98afa0..6fc475a5db61 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -204,6 +204,8 @@ i915_param_named_unsafe(request_timeout_ms, uint, 0600,
>   
>   i915_param_named_unsafe(lmem_size, uint, 0400,
>   			"Set the lmem size(in MiB) for each region. (default: 0, all memory)");
> +i915_param_named_unsafe(lmem_bar_size, uint, 0400,
> +			"Set the lmem bar size(in MiB).");
>   
>   static __always_inline void _print_param(struct drm_printer *p,
>   					 const char *name,
> diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
> index b5e7ea45d191..2733cb6cfe09 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -74,6 +74,7 @@ struct drm_printer;
>   	param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
>   	param(unsigned int, request_timeout_ms, CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 0600 : 0) \
>   	param(unsigned int, lmem_size, 0, 0400) \
> +	param(unsigned int, lmem_bar_size, 0, 0400) \
>   	/* leave bools at the end to not create holes */ \
>   	param(bool, enable_hangcheck, true, 0600) \
>   	param(bool, load_detect_test, false, 0600) \
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Tel: +49 89 99 8853-0, www.intel.de <http://www.intel.de>
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  parent reply	other threads:[~2022-07-11 14:03 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-10 17:29 [Intel-gfx] [PATCH v4 0/2] Add support for LMEM PCIe resizable bar priyanka.dandamudi
2022-07-10 17:29 ` [Intel-gfx] [PATCH v4 1/2] drm/i915: " priyanka.dandamudi
2022-07-10 19:51   ` kernel test robot
2022-07-10 19:51   ` kernel test robot
2022-07-11 13:50   ` Das, Nirmoy
2022-07-10 17:29 ` [Intel-gfx] [PATCH v4 2/2] drm/i915: Add lmem_bar_size modparam priyanka.dandamudi
2022-07-10 20:01   ` kernel test robot
2022-07-11  1:31   ` kernel test robot
2022-07-11 14:03   ` Das, Nirmoy [this message]
2022-07-10 17:59 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for LMEM PCIe resizable bar Patchwork
2022-07-10 17:59 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-07-10 18:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-07-10 19:48 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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