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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On 9/10/2026 11:22 AM, Shawn Guo wrote: >> const struct qmp_phy_cfg *cfg = qmp->cfg; >> >> - reset_control_bulk_assert(qmp->cfg->num_nocsr_resets, qmp->nocsr_resets); >> + if (qmp->nocsr_resets) >> + reset_control_bulk_assert(qmp->cfg->num_nocsr_resets, qmp->nocsr_resets); >> + if (qmp->resets) >> + reset_control_bulk_assert(cfg->num_resets, qmp->resets); >> >> clk_bulk_disable_unprepare(qmp->cfg->num_clks, qmp->clks); >> regulator_bulk_disable(cfg->num_vregs, qmp->vregs); >> @@ -335,6 +1067,20 @@ static int qmp_pcie_power_on(struct phy *phy) >> goto err_disable_pipe_clk; >> } >> >> + if (!qmp->skip_init) { >> + qmp_pcie_init_port_registers(qmp); > Have we tested the patch on Glymur? As Glymur's cfgs have either .pll_tbls > nor .tbls, so skip_init is unconditionally false for Glymur. Is it > intentional to run qmp_pcie_init_port_registers() on Glymur? Thanks for the catch, I will test for glymur before posting next series. > >> + >> + for (i = 0; i < cfg->num_regs; i++) { >> + qphy_clrbits(qmp->base[i] + offs->pcs, >> + cfg->regs[QPHY_PCS_SW_RESET], SW_RESET); >> + qphy_setbits(qmp->base[i] + offs->pcs, >> + cfg->regs[QPHY_PCS_START_CONTROL], >> + SERDES_START | PCS_START); >> + } >> + >> + usleep_range(2000, 2500); >> + } >> + >> for (i = 0; i < cfg->num_regs; i++) { >> status = qmp->base[i] + offs->pcs + cfg->regs[QPHY_PCS_STATUS]; >> ret = readl_poll_timeout(status, val, !(val & cfg->phy_status), 200, >> @@ -357,9 +1103,36 @@ static int qmp_pcie_power_on(struct phy *phy) >> static int qmp_pcie_power_off(struct phy *phy) >> { >> struct qmp_pcie *qmp = phy_get_drvdata(phy); >> + const struct qmp_phy_cfg *cfg = qmp->cfg; >> + const struct qmp_pcie_offsets *offs = cfg->offsets; >> + int i; >> >> clk_bulk_disable_unprepare(qmp->cfg->num_pipe_clks, qmp->pipe_clks); >> >> + /* >> + * While powering off the PHY, only nocsr_resets needs to be checked. >> + * This way, no matter whether the PHY settings were initially >> + * programmed by the bootloader or the PHY driver itself, we can >> + * reuse them the next time the PHY is powered on. >> + */ >> + if (cfg->pll_tbls && !qmp->nocsr_resets) { > Every cfg in the file (Glymur and all seven Nord ones) declares > nocsr_reset_list, and qmp_pcie_reset_init() only leaves qmp->nocsr_resets > NULL when num_nocsr_resets == 0. So the condition is always false, no? Thats true for current targets, but on future targets it might not be true. I will remove the check here for now, in future if we have any target with nocsr then we can add it back. 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Wed, 16 Sep 2026 06:26:58 -0700 (PDT) X-Received: by 2002:a05:6a00:3c86:b0:86d:c2d4:f3c0 with SMTP id d2e1a72fcca58-872376bd23bmr5118933b3a.9.1789565218017; Wed, 16 Sep 2026 06:26:58 -0700 (PDT) Received: from [10.92.206.34] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-87201d17e76sm1241562b3a.49.2026.09.16.06.26.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 16 Sep 2026 06:26:57 -0700 (PDT) Message-ID: <5f862178-ba18-4b27-b5db-1732d57d7b47@oss.qualcomm.com> Date: Wed, 16 Sep 2026 18:56:50 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 5/5] phy: qcom: qmp-pcie: Add Nord Gen5x16 PCIe multi-PHY support To: Shawn Guo Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Bjorn Andersson , Maxime Chevallier , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org References: <20260909-nord-v3-0-b0a82721c547@oss.qualcomm.com> <20260909-nord-v3-5-b0a82721c547@oss.qualcomm.com> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: uOD8qIih1HsEZKPhAWfhW4yLvmvdYfLc X-Authority-Analysis: v=2.4 cv=NelzRGD4 c=1 sm=1 tr=0 ts=6aaa9923 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=L3-XMscUPCAweoWNVT8A:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: uOD8qIih1HsEZKPhAWfhW4yLvmvdYfLc X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE2MDE3OSBTYWx0ZWRfX+VQwSZhTRZg8 OxtoVeRMO/04h7BYCeEAC1s9REoEEhiEkyva5L84yJSy3AtUUSdlonlc8vDcWBWUbB+ePypf59W hhp73BuVZfw6j9I3llxthhlujzBtTeupDsREuk2GYyWy3e8RR0wuygnkp81TXQByxC+Yn6fSRMe wwARnLlNssWi47uR+iKGf+w8sSqC+UZeSPxHnGg2+5PV3yVmEfycfpEUCU3PgyaEUWOxy0ty4rX VpiBWpo8fYstAzqNb/ie6W1iORiJSXxNKWKuM9tXlHZ6FfY4cH6KpFZQCfjjD74w5nXE7kmFJFG NUVMD+1U+EleQfLxzETGRGfpD7BZ/HDflTwDNoknQeMrxmRofp7ckoYU/hMZWGcnvTkXgdEsZrP 44uriQnSOSS6pD9y4B0Ag3Mm00kxDbA6hiClMESI+3JgXjR4lPWJRmWU4Fn4XGUzozTIV7O3Ky7 4XGFpfkgLbJzFgvPh0w== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE2MDE3OSBTYWx0ZWRfX7gcULddLrofX ZaP5d+T51HEqJw/CAOd+5euYwCtBSSFfCAv0+dpGIVQLgxEP/MjBvumTNr+xs3h3i90LUcmmBqE 2f3sb7YeHUPdXIVVWRVZRcmCaCums9w= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-16_02,2026-09-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 impostorscore=0 spamscore=0 clxscore=1015 bulkscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609160179 On 9/10/2026 11:22 AM, Shawn Guo wrote: >> const struct qmp_phy_cfg *cfg = qmp->cfg; >> >> - reset_control_bulk_assert(qmp->cfg->num_nocsr_resets, qmp->nocsr_resets); >> + if (qmp->nocsr_resets) >> + reset_control_bulk_assert(qmp->cfg->num_nocsr_resets, qmp->nocsr_resets); >> + if (qmp->resets) >> + reset_control_bulk_assert(cfg->num_resets, qmp->resets); >> >> clk_bulk_disable_unprepare(qmp->cfg->num_clks, qmp->clks); >> regulator_bulk_disable(cfg->num_vregs, qmp->vregs); >> @@ -335,6 +1067,20 @@ static int qmp_pcie_power_on(struct phy *phy) >> goto err_disable_pipe_clk; >> } >> >> + if (!qmp->skip_init) { >> + qmp_pcie_init_port_registers(qmp); > Have we tested the patch on Glymur? As Glymur's cfgs have either .pll_tbls > nor .tbls, so skip_init is unconditionally false for Glymur. Is it > intentional to run qmp_pcie_init_port_registers() on Glymur? Thanks for the catch, I will test for glymur before posting next series. > >> + >> + for (i = 0; i < cfg->num_regs; i++) { >> + qphy_clrbits(qmp->base[i] + offs->pcs, >> + cfg->regs[QPHY_PCS_SW_RESET], SW_RESET); >> + qphy_setbits(qmp->base[i] + offs->pcs, >> + cfg->regs[QPHY_PCS_START_CONTROL], >> + SERDES_START | PCS_START); >> + } >> + >> + usleep_range(2000, 2500); >> + } >> + >> for (i = 0; i < cfg->num_regs; i++) { >> status = qmp->base[i] + offs->pcs + cfg->regs[QPHY_PCS_STATUS]; >> ret = readl_poll_timeout(status, val, !(val & cfg->phy_status), 200, >> @@ -357,9 +1103,36 @@ static int qmp_pcie_power_on(struct phy *phy) >> static int qmp_pcie_power_off(struct phy *phy) >> { >> struct qmp_pcie *qmp = phy_get_drvdata(phy); >> + const struct qmp_phy_cfg *cfg = qmp->cfg; >> + const struct qmp_pcie_offsets *offs = cfg->offsets; >> + int i; >> >> clk_bulk_disable_unprepare(qmp->cfg->num_pipe_clks, qmp->pipe_clks); >> >> + /* >> + * While powering off the PHY, only nocsr_resets needs to be checked. >> + * This way, no matter whether the PHY settings were initially >> + * programmed by the bootloader or the PHY driver itself, we can >> + * reuse them the next time the PHY is powered on. >> + */ >> + if (cfg->pll_tbls && !qmp->nocsr_resets) { > Every cfg in the file (Glymur and all seven Nord ones) declares > nocsr_reset_list, and qmp_pcie_reset_init() only leaves qmp->nocsr_resets > NULL when num_nocsr_resets == 0. So the condition is always false, no? Thats true for current targets, but on future targets it might not be true. I will remove the check here for now, in future if we have any target with nocsr then we can add it back. Ack for rest of the comments. - Krishna Chaitanya.