From: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
To: Brian Cain <brian.cain@oss.qualcomm.com>, qemu-devel@nongnu.org
Subject: Re: [PATCH 2/5] target/hexagon: check exception_index in has_work
Date: Mon, 19 Oct 2026 14:36:05 -0700 [thread overview]
Message-ID: <5f985341-30fe-4ece-be8a-5a7490dcc8a9@oss.qualcomm.com> (raw)
In-Reply-To: <20261019060911.1479329-3-brian.cain@oss.qualcomm.com>
On 10/18/2026 11:09 PM, Brian Cain wrote:
> Without this check, a halted thread that gets an NMI while
> its modectl E-bit is still set won't wake if no interrupt_request bits
> happen to be pending.
>
> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
> ---
> target/hexagon/cpu.c | 3 +++
> 1 file changed, 3 insertions(+)
>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
next prev parent reply other threads:[~2026-10-19 21:36 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-19 6:09 [PATCH 0/5] Hexagon: enable MTTCG Brian Cain
2026-10-19 6:09 ` [PATCH 1/5] target/hexagon: acquire BQL before reading interrupt state Brian Cain
2026-10-19 21:35 ` Pierrick Bouvier
2026-10-19 6:09 ` [PATCH 2/5] target/hexagon: check exception_index in has_work Brian Cain
2026-10-19 21:36 ` Pierrick Bouvier [this message]
2026-10-19 6:09 ` [PATCH 3/5] target/hexagon: drop a pending HALT when resuming Brian Cain
2026-10-19 21:36 ` Pierrick Bouvier
2026-10-19 6:09 ` [PATCH 4/5] hw/intc: ciad should forward its mask to l2vic Brian Cain
2026-10-19 21:39 ` Pierrick Bouvier
2026-10-19 6:09 ` [PATCH 5/5] target/hexagon: enable MTTCG for system emulation Brian Cain
2026-10-19 21:38 ` Pierrick Bouvier
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