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[187.189.51.143]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-71d725432b6sm295531a34.20.2024.11.28.04.52.36 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Nov 2024 04:52:36 -0800 (PST) Message-ID: <60013b3f-c886-405c-9d32-9834aec0cd2a@linaro.org> Date: Thu, 28 Nov 2024 06:52:33 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 04/11] target/riscv: Support generic CSR indirect access To: qemu-devel@nongnu.org References: <20241117-counter_delegation-v3-0-476d6f36e3c8@rivosinc.com> <20241117-counter_delegation-v3-4-476d6f36e3c8@rivosinc.com> <3db7857b-0987-49f4-b39e-0cf69c3888b0@ventanamicro.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <3db7857b-0987-49f4-b39e-0cf69c3888b0@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::33; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/28/24 05:52, Daniel Henrique Barboza wrote: > > > On 11/17/24 10:15 PM, Atish Patra wrote: >> From: Kaiwen Xue >> >> This adds the indirect access registers required by sscsrind/smcsrind >> and the operations on them. Note that xiselect and xireg are used for >> both AIA and sxcsrind, and the behavior of accessing them depends on >> whether each extension is enabled and the value stored in xiselect. >> >> Co-developed-by: Atish Patra >> Signed-off-by: Atish Patra >> Signed-off-by: Kaiwen Xue >> --- >>   target/riscv/cpu_bits.h |  28 ++++++++- >>   target/riscv/csr.c      | 149 ++++++++++++++++++++++++++++++++++++++++++++++-- >>   2 files changed, 171 insertions(+), 6 deletions(-) >> >> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h >> index 385a2c67c24b..e13c5420a251 100644 >> --- a/target/riscv/cpu_bits.h >> +++ b/target/riscv/cpu_bits.h >> @@ -173,6 +173,13 @@ >>   #define CSR_MISELECT        0x350 >>   #define CSR_MIREG           0x351 >> +/* Machine Indirect Register Alias */ >> +#define CSR_MIREG2          0x352 >> +#define CSR_MIREG3          0x353 >> +#define CSR_MIREG4          0x355 >> +#define CSR_MIREG5          0x356 >> +#define CSR_MIREG6          0x357 >> + >>   /* Machine-Level Interrupts (AIA) */ >>   #define CSR_MTOPEI          0x35c >>   #define CSR_MTOPI           0xfb0 >> @@ -222,6 +229,13 @@ >>   #define CSR_SISELECT        0x150 >>   #define CSR_SIREG           0x151 >> +/* Supervisor Indirect Register Alias */ >> +#define CSR_SIREG2          0x152 >> +#define CSR_SIREG3          0x153 >> +#define CSR_SIREG4          0x155 >> +#define CSR_SIREG5          0x156 >> +#define CSR_SIREG6          0x157 >> + >>   /* Supervisor-Level Interrupts (AIA) */ >>   #define CSR_STOPEI          0x15c >>   #define CSR_STOPI           0xdb0 >> @@ -288,6 +302,13 @@ >>   #define CSR_VSISELECT       0x250 >>   #define CSR_VSIREG          0x251 >> +/* Virtual Supervisor Indirect Alias */ >> +#define CSR_VSIREG2         0x252 >> +#define CSR_VSIREG3         0x253 >> +#define CSR_VSIREG4         0x255 >> +#define CSR_VSIREG5         0x256 >> +#define CSR_VSIREG6         0x257 >> + >>   /* VS-Level Interrupts (H-extension with AIA) */ >>   #define CSR_VSTOPEI         0x25c >>   #define CSR_VSTOPI          0xeb0 >> @@ -863,10 +884,13 @@ typedef enum RISCVException { >>   #define ISELECT_IMSIC_EIE63                0xff >>   #define ISELECT_IMSIC_FIRST                ISELECT_IMSIC_EIDELIVERY >>   #define ISELECT_IMSIC_LAST                 ISELECT_IMSIC_EIE63 >> -#define ISELECT_MASK                       0x1ff >> +#define ISELECT_MASK_AIA                   0x1ff >> + >> +/* MISELECT, SISELECT, and VSISELECT bits (AIA) */ >> +#define ISELECT_MASK_SXCSRIND              0xfff >>   /* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */ >> -#define ISELECT_IMSIC_TOPEI                (ISELECT_MASK + 1) >> +#define ISELECT_IMSIC_TOPEI                (ISELECT_MASK_AIA + 1) >>   /* IMSIC bits (AIA) */ >>   #define IMSIC_TOPEI_IID_SHIFT              16 >> diff --git a/target/riscv/csr.c b/target/riscv/csr.c >> index c91a26a52ef6..57e9c9e25f02 100644 >> --- a/target/riscv/csr.c >> +++ b/target/riscv/csr.c >> @@ -306,6 +306,17 @@ static RISCVException aia_any32(CPURISCVState *env, int csrno) >>       return any32(env, csrno); >>   } >> +static RISCVException csrind_any(CPURISCVState *env, int csrno) >> +{ >> +    RISCVCPU *cpu = env_archcpu(env); > > It is desirable to avoid env_archcpu() calls because it's a bit costly. No, it's not. You're thinking of RISCV_CPU, with the qom dynamic cast assert. env_archcpu is one subtraction. > If you're > doing something else with the RISCVCPU pointer then it is what it is, but if you > want it just to access cpu_cfg you can use riscv_cpu_cfg(env). ... but using riscv_cpu_cfg is still a good idea here. :-) r~