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Mon, 31 Aug 2026 10:55:46 +0000 Message-ID: <6041b95a-ac8c-4410-97cb-8eca51d20d50@amd.com> Date: Mon, 31 Aug 2026 16:25:41 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/7] drm/amd/pm: stage OD reset until commit To: Kevin Wang , amd-gfx@lists.freedesktop.org Cc: alexander.deucher@amd.com, hawking.zhang@amd.com, kenneth.feng@amd.com References: <20260831043507.523599-1-kevin.wang@amd.com> Content-Language: en-US From: "Lazar, Lijo" In-Reply-To: <20260831043507.523599-1-kevin.wang@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: MA1PR01CA0174.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a01:d::12) To SA0PR12MB7091.namprd12.prod.outlook.com (2603:10b6:806:2d5::17) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA0PR12MB7091:EE_|PH7PR12MB6907:EE_ X-MS-Office365-Filtering-Correlation-Id: 78a52db3-76bc-40a8-3065-08df074e68f9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ] > > The pp_od_clk_voltage interface exposes a staged OverDrive workflow: > users edit clock, voltage, and power settings, then write "c" to > commit them to the SMU. > > However, PP_OD_RESTORE_DEFAULT_TABLE does not follow this workflow on > every SMU version. Some backends restore their cached settings and wait > for "c", while others upload the reset table or send frequency-limit > commands directly from "r". As a result, the same userspace sequence > has different hardware effects across ASICs. > > For example: > > - SMU 14.0.0 and SMU 13.0.5 stage reset limits until "c". > - SMU 14.0.2 and SMU 13.0.6 apply reset values immediately. > - Navi10 stages the boot OD table, while Vega20 reads the current SMU > table instead of restoring the saved defaults. > > This series makes "r" restore default values only in driver-side > staging state. "c" remains the sole operation that uploads an OD table > or sends frequency-limit commands to PMFW. > > This gives pp_od_clk_voltage one consistent transaction model: > > edit/reset -> staged driver state -> commit Reset should be reset to defaults and shouldn't require extra commit. This breaks existing userspace for SMU 13.0.6. Thanks, Lijo > It also permits userspace to reset a staged configuration, adjust one > or more settings, and submit the final configuration with one commit, > without temporarily applying an intermediate default configuration. > > Link: https://gitlab.freedesktop.org/drm/amd/-/work_items/5690 > > Kevin Wang (7): > drm/amd/pm: stage od reset for smu 11.0.7 > drm/amd/pm: stage od reset for smu 13.0.2 > drm/amd/pm: stage od reset for smu 13.0.0/13.0.7 > drm/amd/pm: stage od reset for smu 13.0.6 > drm/amd/pm: stage od reset for smu 14.0.2 > drm/amd/pm: stage od reset for smu 15.0.8 > drm/amd/pm: stage od reset for smu vega20 > > .../drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 75 ++++++++++++++-- > .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 2 +- > .../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 15 +--- > .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 +- > .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 85 ++++++++++--------- > .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 2 +- > .../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 2 +- > .../drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c | 50 ++++++----- > 8 files changed, 145 insertions(+), 88 deletions(-) > > -- > 2.55.0 >