From mboxrd@z Thu Jan 1 00:00:00 1970 From: vnkgutta@codeaurora.org Subject: Re: [PATCH v1 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs Date: Fri, 10 Aug 2018 16:03:31 -0700 Message-ID: <6152720eedd8f108c49746942a37813a@codeaurora.org> References: <1533155615-27929-1-git-send-email-vnkgutta@codeaurora.org> <1533155615-27929-4-git-send-email-vnkgutta@codeaurora.org> <20180810035954.GB21528@nazgul.tnic> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20180810035954.GB21528@nazgul.tnic> Sender: linux-kernel-owner@vger.kernel.org To: Borislav Petkov Cc: evgreen@chromium.org, robh@kernel.org, mchehab@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, andy.gross@linaro.org, david.brown@linaro.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, tsoni@codeaurora.org, ckadabi@codeaurora.org, rishabhb@codeaurora.org List-Id: linux-arm-msm@vger.kernel.org On 2018-08-09 20:59, Borislav Petkov wrote: > On Wed, Aug 01, 2018 at 01:33:34PM -0700, Venkata Narendra Kumar Gutta > wrote: >> From: Channagoud Kadabi >> >> Add error reporting driver for SBEs and DBEs. As of now, this driver > > Please write out those abbreviations. Done, I just followed the other commits which has the same and thought they are understood in the community, I'll update it in the next patch set. > >> supports erp for Last Level Cache Controller (LLCC). This driver takes >> care of dumping registers and adding config options to enable and >> disable panic when the errors happen in cache. >> >> Co-developed-by: Venkata Narendra Kumar Gutta >> >> Signed-off-by: Venkata Narendra Kumar Gutta >> Signed-off-by: Channagoud Kadabi > > The proper order is: > > SOB: Author > SOB: Sender/handler/... > > So: > > Signed-off-by: Channagoud Kadabi > Signed-off-by: Venkata Narendra Kumar Gutta Ok, I'll update accordingly. > >> --- >> MAINTAINERS | 7 + >> drivers/edac/Kconfig | 28 +++ >> drivers/edac/Makefile | 1 + >> drivers/edac/qcom_edac.c | 507 >> +++++++++++++++++++++++++++++++++++++++++++++++ >> 4 files changed, 543 insertions(+) >> create mode 100644 drivers/edac/qcom_edac.c >> >> diff --git a/MAINTAINERS b/MAINTAINERS >> index f6a9b08..68b3484 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -5227,6 +5227,13 @@ L: linux-edac@vger.kernel.org >> S: Maintained >> F: drivers/edac/ti_edac.c >> >> +EDAC-QUALCOMM >> +M: Channagoud Kadabi >> +M: Venkata Narendra Kumar Gutta > > Space between name and email address. > >> +L: linux-arm-msm@vger.kernel.org > > Also > > L: linux-edac@vger.kernel.org > > so that the EDAC ML gets CCed too. Ok, Done > >> +S: Maintained >> +F: drivers/edac/qcom_edac.c >> + >> EDIROL UA-101/UA-1000 DRIVER >> M: Clemens Ladisch >> L: alsa-devel@alsa-project.org (moderated for non-subscribers) >> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig >> index 57304b2..c654b0e 100644 >> --- a/drivers/edac/Kconfig >> +++ b/drivers/edac/Kconfig >> @@ -460,4 +460,32 @@ config EDAC_TI >> Support for error detection and correction on the >> TI SoCs. >> >> +config EDAC_QCOM >> + depends on EDAC=y > > Why on EDAC=y? Did you blindly copy it or is there a reason why > edac_core should be only built-in or can it be a module too? I took it from EDAC_ALTERA example. I want to put it like EDAC_QCOM should be dependent on EDAC. Doesn't it make any sense or we don't need this at all? or do you think it's redundant? > >> + tristate "QCOM EDAC Controller" >> + help >> + Support for error detection and correction on the >> + QCOM SoCs. >> + >> +config EDAC_QCOM_LLCC >> + depends on EDAC_QCOM=y && QCOM_LLCC >> + tristate "QCOM EDAC Controller for LLCC Cache" >> + help >> + Support for error detection and correction on the >> + QCOM LLCC cache. Report errors caught by LLCC ECC >> + mechanism. >> + >> + For debugging issues having to do with stability and overall system >> + health, you should probably say 'Y' here. >> + >> +config EDAC_QCOM_LLCC_PANIC_ON_UE >> + depends on EDAC_QCOM_LLCC >> + bool "Panic on uncorrectable errors - qcom llcc" >> + help >> + Forcibly cause a kernel panic if an uncorrectable error (UE) is >> + detected. This can reduce debugging times on hardware which may be >> + operating at voltages or frequencies outside normal specification. >> + >> + For production builds, you should probably say 'N' here. >> + >> endif # EDAC >> diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile >> index 02b43a7..716096d 100644 >> --- a/drivers/edac/Makefile >> +++ b/drivers/edac/Makefile >> @@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA) += altera_edac.o >> obj-$(CONFIG_EDAC_SYNOPSYS) += synopsys_edac.o >> obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o >> obj-$(CONFIG_EDAC_TI) += ti_edac.o >> +obj-$(CONFIG_EDAC_QCOM) += qcom_edac.o >> diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c >> new file mode 100644 >> index 0000000..cf3e2b0 >> --- /dev/null >> +++ b/drivers/edac/qcom_edac.c >> @@ -0,0 +1,507 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Copyright (c) 2018, The Linux Foundation. All rights reserved. >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include "edac_mc.h" >> +#include "edac_device.h" >> + >> +#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE >> +#define LLCC_ERP_PANIC_ON_UE 1 >> +#else >> +#define LLCC_ERP_PANIC_ON_UE 0 >> +#endif >> + >> +#define EDAC_LLCC "qcom_llcc" >> + >> +#define TRP_SYN_REG_CNT 6 >> + >> +#define DRP_SYN_REG_CNT 8 >> + >> +#define LLCC_COMMON_STATUS0 0x0003000C >> +#define LLCC_LB_CNT_MASK GENMASK(31, 28) >> +#define LLCC_LB_CNT_SHIFT 28 >> + >> +/* single & Double Bit syndrome register offsets */ >> +#define TRP_ECC_SB_ERR_SYN0 0x0002304C >> +#define TRP_ECC_DB_ERR_SYN0 0x00020370 >> +#define DRP_ECC_SB_ERR_SYN0 0x0004204C >> +#define DRP_ECC_DB_ERR_SYN0 0x00042070 >> + >> +/* Error register offsets */ >> +#define TRP_ECC_ERROR_STATUS1 0x00020348 >> +#define TRP_ECC_ERROR_STATUS0 0x00020344 >> +#define DRP_ECC_ERROR_STATUS1 0x00042048 >> +#define DRP_ECC_ERROR_STATUS0 0x00042044 >> + >> +/* TRP, DRP interrupt register offsets */ >> +#define DRP_INTERRUPT_STATUS 0x00041000 >> +#define TRP_INTERRUPT_0_STATUS 0x00020480 >> +#define DRP_INTERRUPT_CLEAR 0x00041008 >> +#define DRP_ECC_ERROR_CNTR_CLEAR 0x00040004 >> +#define TRP_INTERRUPT_0_CLEAR 0x00020484 >> +#define TRP_ECC_ERROR_CNTR_CLEAR 0x00020440 >> + >> +/* Mask and shift macros */ >> +#define ECC_DB_ERR_COUNT_MASK GENMASK(4, 0) >> +#define ECC_DB_ERR_WAYS_MASK GENMASK(31, 16) >> +#define ECC_DB_ERR_WAYS_SHIFT BIT(4) >> + >> +#define ECC_SB_ERR_COUNT_MASK GENMASK(23, 16) >> +#define ECC_SB_ERR_COUNT_SHIFT BIT(4) >> +#define ECC_SB_ERR_WAYS_MASK GENMASK(15, 0) >> + >> +#define SB_ECC_ERROR BIT(0) >> +#define DB_ECC_ERROR BIT(1) >> + >> +#define DRP_TRP_INT_CLEAR GENMASK(1, 0) >> +#define DRP_TRP_CNT_CLEAR GENMASK(1, 0) >> + >> +/* Config registers offsets*/ >> +#define DRP_ECC_ERROR_CFG 0x00040000 >> + >> +/* TRP, DRP interrupt register offsets */ >> +#define CMN_INTERRUPT_0_ENABLE 0x0003001C >> +#define CMN_INTERRUPT_2_ENABLE 0x0003003C >> +#define TRP_INTERRUPT_0_ENABLE 0x00020488 >> +#define DRP_INTERRUPT_ENABLE 0x0004100C >> + >> +#define SB_ERROR_THRESHOLD 0x1 >> +#define SB_ERROR_THRESHOLD_SHIFT 24 >> +#define SB_DB_TRP_INTERRUPT_ENABLE 0x3 >> +#define TRP0_INTERRUPT_ENABLE 0x1 >> +#define DRP0_INTERRUPT_ENABLE BIT(6) >> +#define SB_DB_DRP_INTERRUPT_ENABLE 0x3 >> + >> + >> +enum { >> + LLCC_DRAM_CE = 0, >> + LLCC_DRAM_UE, >> + LLCC_TRAM_CE, >> + LLCC_TRAM_UE, >> +}; >> + >> +struct errors_edac { >> + const char *msg; >> + void (*func)(struct edac_device_ctl_info *edev_ctl, >> + int inst_nr, int block_nr, const char *msg); >> +}; >> + >> +static const struct errors_edac errors[] = { >> + {"LLCC Data RAM correctable Error", edac_device_handle_ce}, >> + {"LLCC Data RAM uncorrectable Error", edac_device_handle_ue}, >> + {"LLCC Tag RAM correctable Error", edac_device_handle_ce}, >> + {"LLCC Tag RAM uncorrectable Error", edac_device_handle_ue}, >> +}; > > An array of function pointers just for two functions?! This looks > silly. > Just do a simple if-else. Ok, I'll check and update this one. > >> + >> +static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap) >> +{ >> + u32 sb_err_threshold; >> + int ret; >> + >> + /* Enable TRP in instance 2 of common interrupt enable register */ >> + ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE, >> + TRP0_INTERRUPT_ENABLE, >> + TRP0_INTERRUPT_ENABLE); >> + if (ret) >> + return ret; >> + >> + /* Enable ECC interrupts on Tag Ram */ >> + ret = regmap_update_bits(llcc_bcast_regmap, TRP_INTERRUPT_0_ENABLE, >> + SB_DB_TRP_INTERRUPT_ENABLE, >> + SB_DB_TRP_INTERRUPT_ENABLE); >> + if (ret) >> + return ret; >> + >> + /* Enable SB error for Data RAM */ >> + sb_err_threshold = (SB_ERROR_THRESHOLD << SB_ERROR_THRESHOLD_SHIFT); >> + ret = regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG, >> + sb_err_threshold); >> + if (ret) >> + return ret; >> + >> + /* Enable DRP in instance 2 of common interrupt enable register */ >> + ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE, >> + DRP0_INTERRUPT_ENABLE, >> + DRP0_INTERRUPT_ENABLE); >> + if (ret) >> + return ret; >> + >> + /* Enable ECC interrupts on Data Ram */ >> + ret = regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE, >> + SB_DB_DRP_INTERRUPT_ENABLE); >> + return ret; >> +} >> + >> +/* Clear the error interrupt and counter registers */ >> +static int qcom_llcc_clear_errors(int err_type, struct llcc_drv_data >> *drv) >> +{ >> + int ret = 0; >> + >> + switch (err_type) { >> + case LLCC_DRAM_CE: >> + case LLCC_DRAM_UE: >> + /* Clear the interrupt */ >> + ret = regmap_write(drv->bcast_regmap, DRP_INTERRUPT_CLEAR, >> + DRP_TRP_INT_CLEAR); >> + if (ret) >> + return ret; >> + >> + /* Clear the counters */ >> + ret = regmap_write(drv->bcast_regmap, DRP_ECC_ERROR_CNTR_CLEAR, >> + DRP_TRP_CNT_CLEAR); >> + if (ret) >> + return ret; >> + break; >> + case LLCC_TRAM_CE: >> + case LLCC_TRAM_UE: >> + ret = regmap_write(drv->bcast_regmap, TRP_INTERRUPT_0_CLEAR, >> + DRP_TRP_INT_CLEAR); >> + if (ret) >> + return ret; >> + >> + ret = regmap_write(drv->bcast_regmap, TRP_ECC_ERROR_CNTR_CLEAR, >> + DRP_TRP_CNT_CLEAR); >> + if (ret) >> + return ret; >> + break; >> + } >> + return ret; >> +} >> + >> +/* Dump syndrome registers for tag Ram Double bit errors */ >> +static int dump_trp_db_syn_reg(struct llcc_drv_data *drv, u32 bank) >> +{ >> + int db_err_cnt, db_err_ways, ret, i; >> + u32 synd_reg, synd_val; >> + >> + for (i = 0; i < TRP_SYN_REG_CNT; i++) { >> + synd_reg = TRP_ECC_DB_ERR_SYN0 + (i * 4); >> + ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg, >> + &synd_val); >> + if (ret) >> + return ret; >> + edac_printk(KERN_CRIT, EDAC_LLCC, "TRP_ECC_SYN%d: 0x%8x\n", >> + i, synd_val); >> + } >> + >> + ret = regmap_read(drv->regmap, >> + drv->offsets[bank] + TRP_ECC_ERROR_STATUS1, >> + &db_err_cnt); >> + if (ret) >> + return ret; >> + db_err_cnt = (db_err_cnt & ECC_DB_ERR_COUNT_MASK); >> + edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error count: 0x%4x\n", >> + db_err_cnt); >> + >> + ret = regmap_read(drv->regmap, >> + drv->offsets[bank] + TRP_ECC_ERROR_STATUS0, >> + &db_err_ways); >> + if (ret) >> + return ret; >> + db_err_ways = (db_err_ways & ECC_DB_ERR_WAYS_MASK); >> + db_err_ways >>= ECC_DB_ERR_WAYS_SHIFT; >> + >> + edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error ways: 0x%4x\n", >> + db_err_ways); >> + >> + return ret; >> +} >> + >> +/* Dump syndrome register for tag Ram Single Bit Errors */ >> +static int dump_trp_sb_syn_reg(struct llcc_drv_data *drv, u32 bank) >> +{ >> + int sb_err_cnt, sb_err_ways, ret, i; >> + u32 synd_reg, synd_val; >> + >> + for (i = 0; i < TRP_SYN_REG_CNT; i++) { >> + synd_reg = TRP_ECC_SB_ERR_SYN0 + (i * 4); >> + ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg, >> + &synd_val); >> + if (ret) >> + return ret; >> + edac_printk(KERN_CRIT, EDAC_LLCC, "TRP_ECC_SYN%d: 0x%8x\n", i, >> + synd_val); >> + } >> + >> + ret = regmap_read(drv->regmap, >> + drv->offsets[bank] + TRP_ECC_ERROR_STATUS1, >> + &sb_err_cnt); >> + if (ret) >> + return ret; >> + sb_err_cnt = (sb_err_cnt & ECC_SB_ERR_COUNT_MASK); >> + sb_err_cnt >>= ECC_SB_ERR_COUNT_SHIFT; >> + edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error count: 0x%4x\n", >> + sb_err_cnt); >> + >> + ret = regmap_read(drv->regmap, >> + drv->offsets[bank] + TRP_ECC_ERROR_STATUS0, >> + &sb_err_ways); >> + if (ret) >> + return ret; >> + >> + sb_err_ways = sb_err_ways & ECC_SB_ERR_WAYS_MASK; >> + >> + edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error ways: 0x%4x\n", >> + sb_err_ways); >> + >> + return ret; >> +} >> + >> +/* Dump syndrome registers for Data Ram Double bit errors */ >> +static int dump_drp_db_syn_reg(struct llcc_drv_data *drv, u32 bank) >> +{ >> + int db_err_cnt, db_err_ways, ret, i; >> + u32 synd_reg, synd_val; >> + >> + for (i = 0; i < DRP_SYN_REG_CNT; i++) { >> + synd_reg = DRP_ECC_DB_ERR_SYN0 + (i * 4); >> + ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg, >> + &synd_val); >> + if (ret) >> + return ret; >> + edac_printk(KERN_CRIT, EDAC_LLCC, "DRP_ECC_SYN%d: 0x%8x\n", i, >> + synd_val); >> + } >> + >> + ret = regmap_read(drv->regmap, >> + drv->offsets[bank] + DRP_ECC_ERROR_STATUS1, >> + &db_err_cnt); >> + if (ret) >> + return ret; >> + db_err_cnt = (db_err_cnt & ECC_DB_ERR_COUNT_MASK); >> + edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error count: 0x%4x\n", >> + db_err_cnt); >> + >> + ret = regmap_read(drv->regmap, >> + drv->offsets[bank] + DRP_ECC_ERROR_STATUS0, >> + &db_err_ways); >> + if (ret) >> + return ret; >> + db_err_ways &= ECC_DB_ERR_WAYS_MASK; >> + db_err_ways >>= ECC_DB_ERR_WAYS_SHIFT; >> + edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error ways: 0x%4x\n", >> + db_err_ways); >> + >> + return ret; >> +} >> + >> +/* Dump Syndrome registers for Data Ram Single bit errors*/ >> +static int dump_drp_sb_syn_reg(struct llcc_drv_data *drv, u32 bank) >> +{ >> + int sb_err_cnt, sb_err_ways, ret, i; >> + u32 synd_reg, synd_val; >> + >> + for (i = 0; i < DRP_SYN_REG_CNT; i++) { >> + synd_reg = DRP_ECC_SB_ERR_SYN0 + (i * 4); >> + ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg, >> + &synd_val); >> + if (ret) >> + return ret; >> + edac_printk(KERN_CRIT, EDAC_LLCC, "DRP_ECC_SYN%d: 0x%8x\n", i, >> + synd_val); >> + } >> + >> + ret = regmap_read(drv->regmap, >> + drv->offsets[bank] + DRP_ECC_ERROR_STATUS1, >> + &sb_err_cnt); >> + if (ret) >> + return ret; >> + sb_err_cnt &= ECC_SB_ERR_COUNT_MASK; >> + sb_err_cnt >>= ECC_SB_ERR_COUNT_SHIFT; >> + edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error count: 0x%4x\n", >> + sb_err_cnt); >> + >> + ret = regmap_read(drv->regmap, >> + drv->offsets[bank] + DRP_ECC_ERROR_STATUS0, >> + &sb_err_ways); >> + if (ret) >> + return ret; >> + sb_err_ways = sb_err_ways & ECC_SB_ERR_WAYS_MASK; >> + >> + edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error ways: 0x%4x\n", >> + sb_err_ways); >> + >> + return ret; >> +} >> + >> +static int dump_syn_reg(struct edac_device_ctl_info *edev_ctl, >> + int err_type, u32 bank) >> +{ >> + struct llcc_drv_data *drv = edev_ctl->pvt_info; >> + int ret = 0; >> + >> + switch (err_type) { >> + case LLCC_DRAM_CE: >> + ret = dump_drp_sb_syn_reg(drv, bank); >> + break; >> + case LLCC_DRAM_UE: >> + ret = dump_drp_db_syn_reg(drv, bank); >> + break; >> + case LLCC_TRAM_CE: >> + ret = dump_trp_sb_syn_reg(drv, bank); >> + break; >> + case LLCC_TRAM_UE: >> + ret = dump_trp_db_syn_reg(drv, bank); > > So those functions look very similar to one another and thus are > quadrupled object code. You could have one function instead and pass > in the register as an arg. Or some other smarter scheme to save object > size... There are actually 6 different registers foe each case handled in each function, that's why we had to have different functions with the same outline. I can explore the way of having a single method and categorize based on the error type. But I don't think I will be reducing a lot of object code. Let me explore on what can I do on this. > >> + break; >> + } >> + if (ret) >> + return ret; >> + >> + ret = qcom_llcc_clear_errors(err_type, drv); >> + if (ret) >> + return ret; >> + >> + errors[err_type].func(edev_ctl, 0, bank, errors[err_type].msg); >> + >> + return ret; >> +} >> + >> +static irqreturn_t >> +llcc_ecc_irq_handler (int irq, void *edev_ctl) > > Stray " " after function name. I'll correct this. > >> +{ >> + struct edac_device_ctl_info *edac_dev_ctl; >> + irqreturn_t irq_rc = IRQ_NONE; >> + u32 drp_error, trp_error, i; >> + struct llcc_drv_data *drv; >> + int ret; >> + >> + edac_dev_ctl = (struct edac_device_ctl_info *)edev_ctl; >> + drv = edac_dev_ctl->pvt_info; >> + >> + for (i = 0; i < drv->num_banks; i++) { >> + /* Look for Data RAM errors */ >> + ret = regmap_read(drv->regmap, >> + drv->offsets[i] + DRP_INTERRUPT_STATUS, >> + &drp_error); >> + if (ret) >> + return irq_rc; >> + >> + if (drp_error & SB_ECC_ERROR) { >> + edac_printk(KERN_CRIT, EDAC_LLCC, >> + "Single Bit Error detected in Data Ram\n"); >> + dump_syn_reg(edev_ctl, LLCC_DRAM_CE, i); >> + irq_rc = IRQ_HANDLED; >> + } else if (drp_error & DB_ECC_ERROR) { >> + edac_printk(KERN_CRIT, EDAC_LLCC, >> + "Double Bit Error detected in Data Ram\n"); >> + dump_syn_reg(edev_ctl, LLCC_DRAM_UE, i); >> + irq_rc = IRQ_HANDLED; >> + } >> + >> + /* Look for Tag RAM errors */ >> + ret = regmap_read(drv->regmap, >> + drv->offsets[i] + TRP_INTERRUPT_0_STATUS, >> + &trp_error); >> + if (ret) >> + return irq_rc; >> + if (trp_error & SB_ECC_ERROR) { >> + edac_printk(KERN_CRIT, EDAC_LLCC, >> + "Single Bit Error detected in Tag Ram\n"); >> + dump_syn_reg(edev_ctl, LLCC_TRAM_CE, i); >> + irq_rc = IRQ_HANDLED; >> + } else if (trp_error & DB_ECC_ERROR) { >> + edac_printk(KERN_CRIT, EDAC_LLCC, >> + "Double Bit Error detected in Tag Ram\n"); >> + dump_syn_reg(edev_ctl, LLCC_TRAM_UE, i); >> + irq_rc = IRQ_HANDLED; >> + } >> + } >> + >> + return irq_rc; >> +} >> + >> +static int qcom_llcc_edac_probe(struct platform_device *pdev) >> +{ >> + struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data; >> + struct edac_device_ctl_info *edev_ctl; >> + struct device *dev = &pdev->dev; >> + u32 ecc_irq; >> + int rc; >> + >> + rc = qcom_llcc_core_setup(llcc_driv_data->bcast_regmap); >> + if (rc) >> + return rc; >> + >> + /* Allocate edac control info */ >> + edev_ctl = edac_device_alloc_ctl_info(0, "qcom-llcc", 1, "bank", >> + llcc_driv_data->num_banks, 1, >> + NULL, 0, >> + edac_device_alloc_index()); >> + >> + if (!edev_ctl) >> + return -ENOMEM; >> + >> + edev_ctl->dev = dev; >> + edev_ctl->mod_name = dev_name(dev); >> + edev_ctl->dev_name = dev_name(dev); >> + edev_ctl->ctl_name = "llcc"; >> + edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE; >> + >> + edev_ctl->pvt_info = (struct llcc_drv_data *) llcc_driv_data; > > Why is that cast needed? Not needed, redundant, the variable is already of that type. I'll check if the cast is needed in the first line of this function. From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v1,3/4] drivers: edac: Add EDAC driver support for QCOM SoCs From: Venkata Narendra Kumar Gutta Message-Id: <6152720eedd8f108c49746942a37813a@codeaurora.org> Date: Fri, 10 Aug 2018 16:03:31 -0700 To: Borislav Petkov Cc: evgreen@chromium.org, robh@kernel.org, mchehab@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, andy.gross@linaro.org, david.brown@linaro.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, tsoni@codeaurora.org, ckadabi@codeaurora.org, rishabhb@codeaurora.org List-ID: T24gMjAxOC0wOC0wOSAyMDo1OSwgQm9yaXNsYXYgUGV0a292IHdyb3RlOgo+IE9uIFdlZCwgQXVn IDAxLCAyMDE4IGF0IDAxOjMzOjM0UE0gLTA3MDAsIFZlbmthdGEgTmFyZW5kcmEgS3VtYXIgR3V0 dGEgCj4gd3JvdGU6Cj4+IEZyb206IENoYW5uYWdvdWQgS2FkYWJpIDxja2FkYWJpQGNvZGVhdXJv cmEub3JnPgo+PiAKPj4gQWRkIGVycm9yIHJlcG9ydGluZyBkcml2ZXIgZm9yIFNCRXMgYW5kIERC RXMuIEFzIG9mIG5vdywgdGhpcyBkcml2ZXIKPiAKPiBQbGVhc2Ugd3JpdGUgb3V0IHRob3NlIGFi YnJldmlhdGlvbnMuCkRvbmUsIEkganVzdCBmb2xsb3dlZCB0aGUgb3RoZXIgY29tbWl0cyB3aGlj aCBoYXMgdGhlIHNhbWUgYW5kIHRob3VnaHQgCnRoZXkgYXJlIHVuZGVyc3Rvb2QgaW4gdGhlIGNv bW11bml0eSwKSSdsbCB1cGRhdGUgaXQgaW4gdGhlIG5leHQgcGF0Y2ggc2V0Lgo+IAo+PiBzdXBw b3J0cyBlcnAgZm9yIExhc3QgTGV2ZWwgQ2FjaGUgQ29udHJvbGxlciAoTExDQykuIFRoaXMgZHJp dmVyIHRha2VzCj4+IGNhcmUgb2YgZHVtcGluZyByZWdpc3RlcnMgYW5kIGFkZGluZyBjb25maWcg b3B0aW9ucyB0byBlbmFibGUgYW5kCj4+IGRpc2FibGUgcGFuaWMgd2hlbiB0aGUgZXJyb3JzIGhh cHBlbiBpbiBjYWNoZS4KPj4gCj4+IENvLWRldmVsb3BlZC1ieTogVmVua2F0YSBOYXJlbmRyYSBL dW1hciBHdXR0YSAKPj4gPHZua2d1dHRhQGNvZGVhdXJvcmEub3JnPgo+PiBTaWduZWQtb2ZmLWJ5 OiBWZW5rYXRhIE5hcmVuZHJhIEt1bWFyIEd1dHRhIDx2bmtndXR0YUBjb2RlYXVyb3JhLm9yZz4K Pj4gU2lnbmVkLW9mZi1ieTogQ2hhbm5hZ291ZCBLYWRhYmkgPGNrYWRhYmlAY29kZWF1cm9yYS5v cmc+Cj4gCj4gVGhlIHByb3BlciBvcmRlciBpczoKPiAKPiBTT0I6IEF1dGhvcgo+IFNPQjogU2Vu ZGVyL2hhbmRsZXIvLi4uCj4gCj4gU286Cj4gCj4gU2lnbmVkLW9mZi1ieTogQ2hhbm5hZ291ZCBL YWRhYmkgPGNrYWRhYmlAY29kZWF1cm9yYS5vcmc+Cj4gU2lnbmVkLW9mZi1ieTogVmVua2F0YSBO YXJlbmRyYSBLdW1hciBHdXR0YSA8dm5rZ3V0dGFAY29kZWF1cm9yYS5vcmc+Ck9rLCBJJ2xsIHVw ZGF0ZSBhY2NvcmRpbmdseS4KCj4gCj4+IC0tLQo+PiAgTUFJTlRBSU5FUlMgICAgICAgICAgICAg IHwgICA3ICsKPj4gIGRyaXZlcnMvZWRhYy9LY29uZmlnICAgICB8ICAyOCArKysKPj4gIGRyaXZl cnMvZWRhYy9NYWtlZmlsZSAgICB8ICAgMSArCj4+ICBkcml2ZXJzL2VkYWMvcWNvbV9lZGFjLmMg fCA1MDcgCj4+ICsrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysr Cj4+ICA0IGZpbGVzIGNoYW5nZWQsIDU0MyBpbnNlcnRpb25zKCspCj4+ICBjcmVhdGUgbW9kZSAx MDA2NDQgZHJpdmVycy9lZGFjL3Fjb21fZWRhYy5jCj4+IAo+PiBkaWZmIC0tZ2l0IGEvTUFJTlRB SU5FUlMgYi9NQUlOVEFJTkVSUwo+PiBpbmRleCBmNmE5YjA4Li42OGIzNDg0IDEwMDY0NAo+PiAt LS0gYS9NQUlOVEFJTkVSUwo+PiArKysgYi9NQUlOVEFJTkVSUwo+PiBAQCAtNTIyNyw2ICs1MjI3 LDEzIEBAIEw6CWxpbnV4LWVkYWNAdmdlci5rZXJuZWwub3JnCj4+ICBTOglNYWludGFpbmVkCj4+ ICBGOglkcml2ZXJzL2VkYWMvdGlfZWRhYy5jCj4+IAo+PiArRURBQy1RVUFMQ09NTQo+PiArTToJ Q2hhbm5hZ291ZCBLYWRhYmk8Y2thZGFiaUBjb2RlYXVyb3JhLm9yZz4KPj4gK006CVZlbmthdGEg TmFyZW5kcmEgS3VtYXIgR3V0dGE8dm5rZ3V0dGFAY29kZWF1cm9yYS5vcmc+Cj4gCj4gU3BhY2Ug YmV0d2VlbiBuYW1lIGFuZCBlbWFpbCBhZGRyZXNzLgo+IAo+PiArTDoJbGludXgtYXJtLW1zbUB2 Z2VyLmtlcm5lbC5vcmcKPiAKPiBBbHNvCj4gCj4gTDogICAgICBsaW51eC1lZGFjQHZnZXIua2Vy bmVsLm9yZwo+IAo+IHNvIHRoYXQgdGhlIEVEQUMgTUwgZ2V0cyBDQ2VkIHRvby4KT2ssIERvbmUK PiAKPj4gK1M6CU1haW50YWluZWQKPj4gK0Y6CWRyaXZlcnMvZWRhYy9xY29tX2VkYWMuYwo+PiAr Cj4+ICBFRElST0wgVUEtMTAxL1VBLTEwMDAgRFJJVkVSCj4+ICBNOglDbGVtZW5zIExhZGlzY2gg PGNsZW1lbnNAbGFkaXNjaC5kZT4KPj4gIEw6CWFsc2EtZGV2ZWxAYWxzYS1wcm9qZWN0Lm9yZyAo bW9kZXJhdGVkIGZvciBub24tc3Vic2NyaWJlcnMpCj4+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2Vk YWMvS2NvbmZpZyBiL2RyaXZlcnMvZWRhYy9LY29uZmlnCj4+IGluZGV4IDU3MzA0YjIuLmM2NTRi MGUgMTAwNjQ0Cj4+IC0tLSBhL2RyaXZlcnMvZWRhYy9LY29uZmlnCj4+ICsrKyBiL2RyaXZlcnMv ZWRhYy9LY29uZmlnCj4+IEBAIC00NjAsNCArNDYwLDMyIEBAIGNvbmZpZyBFREFDX1RJCj4+ICAJ ICBTdXBwb3J0IGZvciBlcnJvciBkZXRlY3Rpb24gYW5kIGNvcnJlY3Rpb24gb24gdGhlCj4+ICAg ICAgICAgICAgVEkgU29Dcy4KPj4gCj4+ICtjb25maWcgRURBQ19RQ09NCj4+ICsJZGVwZW5kcyBv biBFREFDPXkKPiAKPiBXaHkgb24gRURBQz15PyBEaWQgeW91IGJsaW5kbHkgY29weSBpdCBvciBp cyB0aGVyZSBhIHJlYXNvbiB3aHkKPiBlZGFjX2NvcmUgc2hvdWxkIGJlIG9ubHkgYnVpbHQtaW4g b3IgY2FuIGl0IGJlIGEgbW9kdWxlIHRvbz8KCkkgdG9vayBpdCBmcm9tIEVEQUNfQUxURVJBIGV4 YW1wbGUuIEkgd2FudCB0byBwdXQgaXQgbGlrZSBFREFDX1FDT00Kc2hvdWxkIGJlIGRlcGVuZGVu dCBvbiBFREFDLiBEb2Vzbid0IGl0IG1ha2UgYW55IHNlbnNlIG9yIHdlIGRvbid0IG5lZWQgCnRo aXMgYXQgYWxsPwpvciBkbyB5b3UgdGhpbmsgaXQncyByZWR1bmRhbnQ/Cgo+IAo+PiArCXRyaXN0 YXRlICJRQ09NIEVEQUMgQ29udHJvbGxlciIKPj4gKwloZWxwCj4+ICsJCVN1cHBvcnQgZm9yIGVy cm9yIGRldGVjdGlvbiBhbmQgY29ycmVjdGlvbiBvbiB0aGUKPj4gKwkJUUNPTSBTb0NzLgo+PiAr Cj4+ICtjb25maWcgRURBQ19RQ09NX0xMQ0MKPj4gKwlkZXBlbmRzIG9uIEVEQUNfUUNPTT15ICYm IFFDT01fTExDQwo+PiArCXRyaXN0YXRlICJRQ09NIEVEQUMgQ29udHJvbGxlciBmb3IgTExDQyBD YWNoZSIKPj4gKwloZWxwCj4+ICsJCVN1cHBvcnQgZm9yIGVycm9yIGRldGVjdGlvbiBhbmQgY29y cmVjdGlvbiBvbiB0aGUKPj4gKwkJUUNPTSBMTENDIGNhY2hlLiBSZXBvcnQgZXJyb3JzIGNhdWdo dCBieSBMTENDIEVDQwo+PiArCQltZWNoYW5pc20uCj4+ICsKPj4gKwkJRm9yIGRlYnVnZ2luZyBp c3N1ZXMgaGF2aW5nIHRvIGRvIHdpdGggc3RhYmlsaXR5IGFuZCBvdmVyYWxsIHN5c3RlbQo+PiAr CQloZWFsdGgsIHlvdSBzaG91bGQgcHJvYmFibHkgc2F5ICdZJyBoZXJlLgo+PiArCj4+ICtjb25m aWcgRURBQ19RQ09NX0xMQ0NfUEFOSUNfT05fVUUKPj4gKwlkZXBlbmRzIG9uIEVEQUNfUUNPTV9M TENDCj4+ICsJYm9vbCAiUGFuaWMgb24gdW5jb3JyZWN0YWJsZSBlcnJvcnMgLSBxY29tIGxsY2Mi Cj4+ICsJaGVscAo+PiArCQlGb3JjaWJseSBjYXVzZSBhIGtlcm5lbCBwYW5pYyBpZiBhbiB1bmNv cnJlY3RhYmxlIGVycm9yIChVRSkgaXMKPj4gKwkJZGV0ZWN0ZWQuIFRoaXMgY2FuIHJlZHVjZSBk ZWJ1Z2dpbmcgdGltZXMgb24gaGFyZHdhcmUgd2hpY2ggbWF5IGJlCj4+ICsJCW9wZXJhdGluZyBh dCB2b2x0YWdlcyBvciBmcmVxdWVuY2llcyBvdXRzaWRlIG5vcm1hbCBzcGVjaWZpY2F0aW9uLgo+ PiArCj4+ICsJCUZvciBwcm9kdWN0aW9uIGJ1aWxkcywgeW91IHNob3VsZCBwcm9iYWJseSBzYXkg J04nIGhlcmUuCj4+ICsKPj4gIGVuZGlmICMgRURBQwo+PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9l ZGFjL01ha2VmaWxlIGIvZHJpdmVycy9lZGFjL01ha2VmaWxlCj4+IGluZGV4IDAyYjQzYTcuLjcx NjA5NmQgMTAwNjQ0Cj4+IC0tLSBhL2RyaXZlcnMvZWRhYy9NYWtlZmlsZQo+PiArKysgYi9kcml2 ZXJzL2VkYWMvTWFrZWZpbGUKPj4gQEAgLTc3LDMgKzc3LDQgQEAgb2JqLSQoQ09ORklHX0VEQUNf QUxURVJBKQkJKz0gYWx0ZXJhX2VkYWMubwo+PiAgb2JqLSQoQ09ORklHX0VEQUNfU1lOT1BTWVMp CQkrPSBzeW5vcHN5c19lZGFjLm8KPj4gIG9iai0kKENPTkZJR19FREFDX1hHRU5FKQkJKz0geGdl bmVfZWRhYy5vCj4+ICBvYmotJChDT05GSUdfRURBQ19USSkJCQkrPSB0aV9lZGFjLm8KPj4gK29i ai0kKENPTkZJR19FREFDX1FDT00pCQkJKz0gcWNvbV9lZGFjLm8KPj4gZGlmZiAtLWdpdCBhL2Ry aXZlcnMvZWRhYy9xY29tX2VkYWMuYyBiL2RyaXZlcnMvZWRhYy9xY29tX2VkYWMuYwo+PiBuZXcg ZmlsZSBtb2RlIDEwMDY0NAo+PiBpbmRleCAwMDAwMDAwLi5jZjNlMmIwCj4+IC0tLSAvZGV2L251 bGwKPj4gKysrIGIvZHJpdmVycy9lZGFjL3Fjb21fZWRhYy5jCj4+IEBAIC0wLDAgKzEsNTA3IEBA Cj4+ICsvLyBTUERYLUxpY2Vuc2UtSWRlbnRpZmllcjogR1BMLTIuMAo+PiArLyoKPj4gKyAqIENv cHlyaWdodCAoYykgMjAxOCwgVGhlIExpbnV4IEZvdW5kYXRpb24uIEFsbCByaWdodHMgcmVzZXJ2 ZWQuCj4+ICsgKi8KPj4gKwo+PiArI2luY2x1ZGUgPGxpbnV4L2tlcm5lbC5oPgo+PiArI2luY2x1 ZGUgPGxpbnV4L2VkYWMuaD4KPj4gKyNpbmNsdWRlIDxsaW51eC9vZl9kZXZpY2UuaD4KPj4gKyNp bmNsdWRlIDxsaW51eC9wbGF0Zm9ybV9kZXZpY2UuaD4KPj4gKyNpbmNsdWRlIDxsaW51eC9zbXAu aD4KPj4gKyNpbmNsdWRlIDxsaW51eC9yZWdtYXAuaD4KPj4gKyNpbmNsdWRlIDxsaW51eC9pbnRl cnJ1cHQuaD4KPj4gKyNpbmNsdWRlIDxsaW51eC9zb2MvcWNvbS9sbGNjLXFjb20uaD4KPj4gKyNp bmNsdWRlICJlZGFjX21jLmgiCj4+ICsjaW5jbHVkZSAiZWRhY19kZXZpY2UuaCIKPj4gKwo+PiAr I2lmZGVmIENPTkZJR19FREFDX1FDT01fTExDQ19QQU5JQ19PTl9VRQo+PiArI2RlZmluZSBMTEND X0VSUF9QQU5JQ19PTl9VRSAgICAgICAgICAgIDEKPj4gKyNlbHNlCj4+ICsjZGVmaW5lIExMQ0Nf RVJQX1BBTklDX09OX1VFICAgICAgICAgICAgMAo+PiArI2VuZGlmCj4+ICsKPj4gKyNkZWZpbmUg RURBQ19MTENDICAgICAgICAgICAgICAgICAgICAgICAicWNvbV9sbGNjIgo+PiArCj4+ICsjZGVm aW5lIFRSUF9TWU5fUkVHX0NOVCAgICAgICAgICAgICAgICAgNgo+PiArCj4+ICsjZGVmaW5lIERS UF9TWU5fUkVHX0NOVCAgICAgICAgICAgICAgICAgOAo+PiArCj4+ICsjZGVmaW5lIExMQ0NfQ09N TU9OX1NUQVRVUzAgICAgICAgICAgICAgMHgwMDAzMDAwQwo+PiArI2RlZmluZSBMTENDX0xCX0NO VF9NQVNLICAgICAgICAgICAgICAgIEdFTk1BU0soMzEsIDI4KQo+PiArI2RlZmluZSBMTENDX0xC X0NOVF9TSElGVCAgICAgICAgICAgICAgIDI4Cj4+ICsKPj4gKy8qIHNpbmdsZSAmIERvdWJsZSBC aXQgc3luZHJvbWUgcmVnaXN0ZXIgb2Zmc2V0cyAqLwo+PiArI2RlZmluZSBUUlBfRUNDX1NCX0VS Ul9TWU4wICAgICAgICAgICAgIDB4MDAwMjMwNEMKPj4gKyNkZWZpbmUgVFJQX0VDQ19EQl9FUlJf U1lOMCAgICAgICAgICAgICAweDAwMDIwMzcwCj4+ICsjZGVmaW5lIERSUF9FQ0NfU0JfRVJSX1NZ TjAgICAgICAgICAgICAgMHgwMDA0MjA0Qwo+PiArI2RlZmluZSBEUlBfRUNDX0RCX0VSUl9TWU4w ICAgICAgICAgICAgIDB4MDAwNDIwNzAKPj4gKwo+PiArLyogRXJyb3IgcmVnaXN0ZXIgb2Zmc2V0 cyAqLwo+PiArI2RlZmluZSBUUlBfRUNDX0VSUk9SX1NUQVRVUzEgICAgICAgICAgIDB4MDAwMjAz NDgKPj4gKyNkZWZpbmUgVFJQX0VDQ19FUlJPUl9TVEFUVVMwICAgICAgICAgICAweDAwMDIwMzQ0 Cj4+ICsjZGVmaW5lIERSUF9FQ0NfRVJST1JfU1RBVFVTMSAgICAgICAgICAgMHgwMDA0MjA0OAo+ PiArI2RlZmluZSBEUlBfRUNDX0VSUk9SX1NUQVRVUzAgICAgICAgICAgIDB4MDAwNDIwNDQKPj4g Kwo+PiArLyogVFJQLCBEUlAgaW50ZXJydXB0IHJlZ2lzdGVyIG9mZnNldHMgKi8KPj4gKyNkZWZp bmUgRFJQX0lOVEVSUlVQVF9TVEFUVVMgICAgICAgICAgICAweDAwMDQxMDAwCj4+ICsjZGVmaW5l IFRSUF9JTlRFUlJVUFRfMF9TVEFUVVMgICAgICAgICAgMHgwMDAyMDQ4MAo+PiArI2RlZmluZSBE UlBfSU5URVJSVVBUX0NMRUFSICAgICAgICAgICAgIDB4MDAwNDEwMDgKPj4gKyNkZWZpbmUgRFJQ X0VDQ19FUlJPUl9DTlRSX0NMRUFSICAgICAgICAweDAwMDQwMDA0Cj4+ICsjZGVmaW5lIFRSUF9J TlRFUlJVUFRfMF9DTEVBUiAgICAgICAgICAgMHgwMDAyMDQ4NAo+PiArI2RlZmluZSBUUlBfRUND X0VSUk9SX0NOVFJfQ0xFQVIgICAgICAgIDB4MDAwMjA0NDAKPj4gKwo+PiArLyogTWFzayBhbmQg c2hpZnQgbWFjcm9zICovCj4+ICsjZGVmaW5lIEVDQ19EQl9FUlJfQ09VTlRfTUFTSyAgICAgICAg ICAgR0VOTUFTSyg0LCAwKQo+PiArI2RlZmluZSBFQ0NfREJfRVJSX1dBWVNfTUFTSyAgICAgICAg ICAgIEdFTk1BU0soMzEsIDE2KQo+PiArI2RlZmluZSBFQ0NfREJfRVJSX1dBWVNfU0hJRlQgICAg ICAgICAgIEJJVCg0KQo+PiArCj4+ICsjZGVmaW5lIEVDQ19TQl9FUlJfQ09VTlRfTUFTSyAgICAg ICAgICAgR0VOTUFTSygyMywgMTYpCj4+ICsjZGVmaW5lIEVDQ19TQl9FUlJfQ09VTlRfU0hJRlQg ICAgICAgICAgQklUKDQpCj4+ICsjZGVmaW5lIEVDQ19TQl9FUlJfV0FZU19NQVNLICAgICAgICAg ICAgR0VOTUFTSygxNSwgMCkKPj4gKwo+PiArI2RlZmluZSBTQl9FQ0NfRVJST1IgICAgICAgICAg ICAgICAgICAgIEJJVCgwKQo+PiArI2RlZmluZSBEQl9FQ0NfRVJST1IgICAgICAgICAgICAgICAg ICAgIEJJVCgxKQo+PiArCj4+ICsjZGVmaW5lIERSUF9UUlBfSU5UX0NMRUFSICAgICAgICAgICAg ICAgR0VOTUFTSygxLCAwKQo+PiArI2RlZmluZSBEUlBfVFJQX0NOVF9DTEVBUiAgICAgICAgICAg ICAgIEdFTk1BU0soMSwgMCkKPj4gKwo+PiArLyogQ29uZmlnIHJlZ2lzdGVycyBvZmZzZXRzKi8K Pj4gKyNkZWZpbmUgRFJQX0VDQ19FUlJPUl9DRkcgICAgICAgICAgICAgICAweDAwMDQwMDAwCj4+ ICsKPj4gKy8qIFRSUCwgRFJQIGludGVycnVwdCByZWdpc3RlciBvZmZzZXRzICovCj4+ICsjZGVm aW5lIENNTl9JTlRFUlJVUFRfMF9FTkFCTEUgICAgICAgICAgMHgwMDAzMDAxQwo+PiArI2RlZmlu ZSBDTU5fSU5URVJSVVBUXzJfRU5BQkxFICAgICAgICAgIDB4MDAwMzAwM0MKPj4gKyNkZWZpbmUg VFJQX0lOVEVSUlVQVF8wX0VOQUJMRSAgICAgICAgICAweDAwMDIwNDg4Cj4+ICsjZGVmaW5lIERS UF9JTlRFUlJVUFRfRU5BQkxFICAgICAgICAgICAgMHgwMDA0MTAwQwo+PiArCj4+ICsjZGVmaW5l IFNCX0VSUk9SX1RIUkVTSE9MRCAgICAgICAgICAgICAgMHgxCj4+ICsjZGVmaW5lIFNCX0VSUk9S X1RIUkVTSE9MRF9TSElGVCAgICAgICAgMjQKPj4gKyNkZWZpbmUgU0JfREJfVFJQX0lOVEVSUlVQ VF9FTkFCTEUgICAgICAweDMKPj4gKyNkZWZpbmUgVFJQMF9JTlRFUlJVUFRfRU5BQkxFICAgICAg ICAgICAweDEKPj4gKyNkZWZpbmUgRFJQMF9JTlRFUlJVUFRfRU5BQkxFICAgICAgICAgICBCSVQo NikKPj4gKyNkZWZpbmUgU0JfREJfRFJQX0lOVEVSUlVQVF9FTkFCTEUgICAgICAweDMKPj4gKwo+ PiArCj4+ICtlbnVtIHsKPj4gKwlMTENDX0RSQU1fQ0UgPSAwLAo+PiArCUxMQ0NfRFJBTV9VRSwK Pj4gKwlMTENDX1RSQU1fQ0UsCj4+ICsJTExDQ19UUkFNX1VFLAo+PiArfTsKPj4gKwo+PiArc3Ry dWN0IGVycm9yc19lZGFjIHsKPj4gKwljb25zdCBjaGFyICptc2c7Cj4+ICsJdm9pZCAoKmZ1bmMp KHN0cnVjdCBlZGFjX2RldmljZV9jdGxfaW5mbyAqZWRldl9jdGwsCj4+ICsJCQkJaW50IGluc3Rf bnIsIGludCBibG9ja19uciwgY29uc3QgY2hhciAqbXNnKTsKPj4gK307Cj4+ICsKPj4gK3N0YXRp YyBjb25zdCBzdHJ1Y3QgZXJyb3JzX2VkYWMgZXJyb3JzW10gPSB7Cj4+ICsJeyJMTENDIERhdGEg UkFNIGNvcnJlY3RhYmxlIEVycm9yIiwgZWRhY19kZXZpY2VfaGFuZGxlX2NlfSwKPj4gKwl7IkxM Q0MgRGF0YSBSQU0gdW5jb3JyZWN0YWJsZSBFcnJvciIsIGVkYWNfZGV2aWNlX2hhbmRsZV91ZX0s Cj4+ICsJeyJMTENDIFRhZyBSQU0gY29ycmVjdGFibGUgRXJyb3IiLCBlZGFjX2RldmljZV9oYW5k bGVfY2V9LAo+PiArCXsiTExDQyBUYWcgUkFNIHVuY29ycmVjdGFibGUgRXJyb3IiLCBlZGFjX2Rl dmljZV9oYW5kbGVfdWV9LAo+PiArfTsKPiAKPiBBbiBhcnJheSBvZiBmdW5jdGlvbiBwb2ludGVy cyBqdXN0IGZvciB0d28gZnVuY3Rpb25zPyEgVGhpcyBsb29rcyAKPiBzaWxseS4KPiBKdXN0IGRv IGEgc2ltcGxlIGlmLWVsc2UuCk9rLCBJJ2xsIGNoZWNrIGFuZCB1cGRhdGUgdGhpcyBvbmUuCj4g Cj4+ICsKPj4gK3N0YXRpYyBpbnQgcWNvbV9sbGNjX2NvcmVfc2V0dXAoc3RydWN0IHJlZ21hcCAq bGxjY19iY2FzdF9yZWdtYXApCj4+ICt7Cj4+ICsJdTMyIHNiX2Vycl90aHJlc2hvbGQ7Cj4+ICsJ aW50IHJldDsKPj4gKwo+PiArCS8qIEVuYWJsZSBUUlAgaW4gaW5zdGFuY2UgMiBvZiBjb21tb24g aW50ZXJydXB0IGVuYWJsZSByZWdpc3RlciAqLwo+PiArCXJldCA9IHJlZ21hcF91cGRhdGVfYml0 cyhsbGNjX2JjYXN0X3JlZ21hcCwgQ01OX0lOVEVSUlVQVF8yX0VOQUJMRSwKPj4gKwkJCQkgVFJQ MF9JTlRFUlJVUFRfRU5BQkxFLAo+PiArCQkJCSBUUlAwX0lOVEVSUlVQVF9FTkFCTEUpOwo+PiAr CWlmIChyZXQpCj4+ICsJCXJldHVybiByZXQ7Cj4+ICsKPj4gKwkvKiBFbmFibGUgRUNDIGludGVy cnVwdHMgb24gVGFnIFJhbSAqLwo+PiArCXJldCA9IHJlZ21hcF91cGRhdGVfYml0cyhsbGNjX2Jj YXN0X3JlZ21hcCwgVFJQX0lOVEVSUlVQVF8wX0VOQUJMRSwKPj4gKwkJCQkgU0JfREJfVFJQX0lO VEVSUlVQVF9FTkFCTEUsCj4+ICsJCQkJIFNCX0RCX1RSUF9JTlRFUlJVUFRfRU5BQkxFKTsKPj4g KwlpZiAocmV0KQo+PiArCQlyZXR1cm4gcmV0Owo+PiArCj4+ICsJLyogRW5hYmxlIFNCIGVycm9y IGZvciBEYXRhIFJBTSAqLwo+PiArCXNiX2Vycl90aHJlc2hvbGQgPSAoU0JfRVJST1JfVEhSRVNI T0xEIDw8IFNCX0VSUk9SX1RIUkVTSE9MRF9TSElGVCk7Cj4+ICsJcmV0ID0gcmVnbWFwX3dyaXRl KGxsY2NfYmNhc3RfcmVnbWFwLCBEUlBfRUNDX0VSUk9SX0NGRywKPj4gKwkJCSAgIHNiX2Vycl90 aHJlc2hvbGQpOwo+PiArCWlmIChyZXQpCj4+ICsJCXJldHVybiByZXQ7Cj4+ICsKPj4gKwkvKiBF bmFibGUgRFJQIGluIGluc3RhbmNlIDIgb2YgY29tbW9uIGludGVycnVwdCBlbmFibGUgcmVnaXN0 ZXIgKi8KPj4gKwlyZXQgPSByZWdtYXBfdXBkYXRlX2JpdHMobGxjY19iY2FzdF9yZWdtYXAsIENN Tl9JTlRFUlJVUFRfMl9FTkFCTEUsCj4+ICsJCQkJIERSUDBfSU5URVJSVVBUX0VOQUJMRSwKPj4g KwkJCQkgRFJQMF9JTlRFUlJVUFRfRU5BQkxFKTsKPj4gKwlpZiAocmV0KQo+PiArCQlyZXR1cm4g cmV0Owo+PiArCj4+ICsJLyogRW5hYmxlIEVDQyBpbnRlcnJ1cHRzIG9uIERhdGEgUmFtICovCj4+ ICsJcmV0ID0gcmVnbWFwX3dyaXRlKGxsY2NfYmNhc3RfcmVnbWFwLCBEUlBfSU5URVJSVVBUX0VO QUJMRSwKPj4gKwkJCSAgIFNCX0RCX0RSUF9JTlRFUlJVUFRfRU5BQkxFKTsKPj4gKwlyZXR1cm4g cmV0Owo+PiArfQo+PiArCj4+ICsvKiBDbGVhciB0aGUgZXJyb3IgaW50ZXJydXB0IGFuZCBjb3Vu dGVyIHJlZ2lzdGVycyAqLwo+PiArc3RhdGljIGludCBxY29tX2xsY2NfY2xlYXJfZXJyb3JzKGlu dCBlcnJfdHlwZSwgc3RydWN0IGxsY2NfZHJ2X2RhdGEgCj4+ICpkcnYpCj4+ICt7Cj4+ICsJaW50 IHJldCA9IDA7Cj4+ICsKPj4gKwlzd2l0Y2ggKGVycl90eXBlKSB7Cj4+ICsJY2FzZSBMTENDX0RS QU1fQ0U6Cj4+ICsJY2FzZSBMTENDX0RSQU1fVUU6Cj4+ICsJCS8qIENsZWFyIHRoZSBpbnRlcnJ1 cHQgKi8KPj4gKwkJcmV0ID0gcmVnbWFwX3dyaXRlKGRydi0+YmNhc3RfcmVnbWFwLCBEUlBfSU5U RVJSVVBUX0NMRUFSLAo+PiArCQkJCSAgIERSUF9UUlBfSU5UX0NMRUFSKTsKPj4gKwkJaWYgKHJl dCkKPj4gKwkJCXJldHVybiByZXQ7Cj4+ICsKPj4gKwkJLyogQ2xlYXIgdGhlIGNvdW50ZXJzICov Cj4+ICsJCXJldCA9IHJlZ21hcF93cml0ZShkcnYtPmJjYXN0X3JlZ21hcCwgRFJQX0VDQ19FUlJP Ul9DTlRSX0NMRUFSLAo+PiArCQkJCSAgIERSUF9UUlBfQ05UX0NMRUFSKTsKPj4gKwkJaWYgKHJl dCkKPj4gKwkJCXJldHVybiByZXQ7Cj4+ICsJCWJyZWFrOwo+PiArCWNhc2UgTExDQ19UUkFNX0NF Ogo+PiArCWNhc2UgTExDQ19UUkFNX1VFOgo+PiArCQlyZXQgPSByZWdtYXBfd3JpdGUoZHJ2LT5i Y2FzdF9yZWdtYXAsIFRSUF9JTlRFUlJVUFRfMF9DTEVBUiwKPj4gKwkJCQkgICBEUlBfVFJQX0lO VF9DTEVBUik7Cj4+ICsJCWlmIChyZXQpCj4+ICsJCQlyZXR1cm4gcmV0Owo+PiArCj4+ICsJCXJl dCA9IHJlZ21hcF93cml0ZShkcnYtPmJjYXN0X3JlZ21hcCwgVFJQX0VDQ19FUlJPUl9DTlRSX0NM RUFSLAo+PiArCQkJCSAgIERSUF9UUlBfQ05UX0NMRUFSKTsKPj4gKwkJaWYgKHJldCkKPj4gKwkJ CXJldHVybiByZXQ7Cj4+ICsJCWJyZWFrOwo+PiArCX0KPj4gKwlyZXR1cm4gcmV0Owo+PiArfQo+ PiArCj4+ICsvKiBEdW1wIHN5bmRyb21lIHJlZ2lzdGVycyBmb3IgdGFnIFJhbSBEb3VibGUgYml0 IGVycm9ycyAqLwo+PiArc3RhdGljIGludCBkdW1wX3RycF9kYl9zeW5fcmVnKHN0cnVjdCBsbGNj X2Rydl9kYXRhICpkcnYsIHUzMiBiYW5rKQo+PiArewo+PiArCWludCBkYl9lcnJfY250LCBkYl9l cnJfd2F5cywgcmV0LCBpOwo+PiArCXUzMiBzeW5kX3JlZywgc3luZF92YWw7Cj4+ICsKPj4gKwlm b3IgKGkgPSAwOyBpIDwgVFJQX1NZTl9SRUdfQ05UOyBpKyspIHsKPj4gKwkJc3luZF9yZWcgPSBU UlBfRUNDX0RCX0VSUl9TWU4wICsgKGkgKiA0KTsKPj4gKwkJcmV0ID0gcmVnbWFwX3JlYWQoZHJ2 LT5yZWdtYXAsIGRydi0+b2Zmc2V0c1tiYW5rXSArIHN5bmRfcmVnLAo+PiArCQkJCSAgJnN5bmRf dmFsKTsKPj4gKwkJaWYgKHJldCkKPj4gKwkJCXJldHVybiByZXQ7Cj4+ICsJCWVkYWNfcHJpbnRr KEtFUk5fQ1JJVCwgRURBQ19MTENDLCAiVFJQX0VDQ19TWU4lZDogMHglOHhcbiIsCj4+ICsJCQkg ICAgaSwgc3luZF92YWwpOwo+PiArCX0KPj4gKwo+PiArCXJldCA9IHJlZ21hcF9yZWFkKGRydi0+ cmVnbWFwLAo+PiArCQkJICBkcnYtPm9mZnNldHNbYmFua10gKyBUUlBfRUNDX0VSUk9SX1NUQVRV UzEsCj4+ICsJCQkgICZkYl9lcnJfY250KTsKPj4gKwlpZiAocmV0KQo+PiArCQlyZXR1cm4gcmV0 Owo+PiArCWRiX2Vycl9jbnQgPSAoZGJfZXJyX2NudCAmIEVDQ19EQl9FUlJfQ09VTlRfTUFTSyk7 Cj4+ICsJZWRhY19wcmludGsoS0VSTl9DUklULCBFREFDX0xMQ0MsICJEb3VibGUtQml0IGVycm9y IGNvdW50OiAweCU0eFxuIiwKPj4gKwkJICAgIGRiX2Vycl9jbnQpOwo+PiArCj4+ICsJcmV0ID0g cmVnbWFwX3JlYWQoZHJ2LT5yZWdtYXAsCj4+ICsJCQkgIGRydi0+b2Zmc2V0c1tiYW5rXSArIFRS UF9FQ0NfRVJST1JfU1RBVFVTMCwKPj4gKwkJCSAgJmRiX2Vycl93YXlzKTsKPj4gKwlpZiAocmV0 KQo+PiArCQlyZXR1cm4gcmV0Owo+PiArCWRiX2Vycl93YXlzID0gKGRiX2Vycl93YXlzICYgRUND X0RCX0VSUl9XQVlTX01BU0spOwo+PiArCWRiX2Vycl93YXlzID4+PSBFQ0NfREJfRVJSX1dBWVNf U0hJRlQ7Cj4+ICsKPj4gKwllZGFjX3ByaW50ayhLRVJOX0NSSVQsIEVEQUNfTExDQywgIkRvdWJs ZS1CaXQgZXJyb3Igd2F5czogMHglNHhcbiIsCj4+ICsJCSAgICBkYl9lcnJfd2F5cyk7Cj4+ICsK Pj4gKwlyZXR1cm4gcmV0Owo+PiArfQo+PiArCj4+ICsvKiBEdW1wIHN5bmRyb21lIHJlZ2lzdGVy IGZvciB0YWcgUmFtIFNpbmdsZSBCaXQgRXJyb3JzICovCj4+ICtzdGF0aWMgaW50IGR1bXBfdHJw X3NiX3N5bl9yZWcoc3RydWN0IGxsY2NfZHJ2X2RhdGEgKmRydiwgdTMyIGJhbmspCj4+ICt7Cj4+ ICsJaW50IHNiX2Vycl9jbnQsIHNiX2Vycl93YXlzLCByZXQsIGk7Cj4+ICsJdTMyIHN5bmRfcmVn LCBzeW5kX3ZhbDsKPj4gKwo+PiArCWZvciAoaSA9IDA7IGkgPCBUUlBfU1lOX1JFR19DTlQ7IGkr Kykgewo+PiArCQlzeW5kX3JlZyA9IFRSUF9FQ0NfU0JfRVJSX1NZTjAgKyAoaSAqIDQpOwo+PiAr CQlyZXQgPSByZWdtYXBfcmVhZChkcnYtPnJlZ21hcCwgZHJ2LT5vZmZzZXRzW2JhbmtdICsgc3lu ZF9yZWcsCj4+ICsJCQkJICAmc3luZF92YWwpOwo+PiArCQlpZiAocmV0KQo+PiArCQkJcmV0dXJu IHJldDsKPj4gKwkJZWRhY19wcmludGsoS0VSTl9DUklULCBFREFDX0xMQ0MsICJUUlBfRUNDX1NZ TiVkOiAweCU4eFxuIiwgaSwKPj4gKwkJCSAgICBzeW5kX3ZhbCk7Cj4+ICsJfQo+PiArCj4+ICsJ cmV0ID0gcmVnbWFwX3JlYWQoZHJ2LT5yZWdtYXAsCj4+ICsJCQkgIGRydi0+b2Zmc2V0c1tiYW5r XSArIFRSUF9FQ0NfRVJST1JfU1RBVFVTMSwKPj4gKwkJCSAgJnNiX2Vycl9jbnQpOwo+PiArCWlm IChyZXQpCj4+ICsJCXJldHVybiByZXQ7Cj4+ICsJc2JfZXJyX2NudCA9IChzYl9lcnJfY250ICYg RUNDX1NCX0VSUl9DT1VOVF9NQVNLKTsKPj4gKwlzYl9lcnJfY250ID4+PSBFQ0NfU0JfRVJSX0NP VU5UX1NISUZUOwo+PiArCWVkYWNfcHJpbnRrKEtFUk5fQ1JJVCwgRURBQ19MTENDLCAiU2luZ2xl LUJpdCBlcnJvciBjb3VudDogMHglNHhcbiIsCj4+ICsJCSAgICBzYl9lcnJfY250KTsKPj4gKwo+ PiArCXJldCA9IHJlZ21hcF9yZWFkKGRydi0+cmVnbWFwLAo+PiArCQkJICBkcnYtPm9mZnNldHNb YmFua10gKyBUUlBfRUNDX0VSUk9SX1NUQVRVUzAsCj4+ICsJCQkgICZzYl9lcnJfd2F5cyk7Cj4+ ICsJaWYgKHJldCkKPj4gKwkJcmV0dXJuIHJldDsKPj4gKwo+PiArCXNiX2Vycl93YXlzID0gc2Jf ZXJyX3dheXMgJiBFQ0NfU0JfRVJSX1dBWVNfTUFTSzsKPj4gKwo+PiArCWVkYWNfcHJpbnRrKEtF Uk5fQ1JJVCwgRURBQ19MTENDLCAiU2luZ2xlLUJpdCBlcnJvciB3YXlzOiAweCU0eFxuIiwKPj4g KwkJICAgIHNiX2Vycl93YXlzKTsKPj4gKwo+PiArCXJldHVybiByZXQ7Cj4+ICt9Cj4+ICsKPj4g Ky8qIER1bXAgc3luZHJvbWUgcmVnaXN0ZXJzIGZvciBEYXRhIFJhbSBEb3VibGUgYml0IGVycm9y cyAqLwo+PiArc3RhdGljIGludCBkdW1wX2RycF9kYl9zeW5fcmVnKHN0cnVjdCBsbGNjX2Rydl9k YXRhICpkcnYsIHUzMiBiYW5rKQo+PiArewo+PiArCWludCBkYl9lcnJfY250LCBkYl9lcnJfd2F5 cywgcmV0LCBpOwo+PiArCXUzMiBzeW5kX3JlZywgc3luZF92YWw7Cj4+ICsKPj4gKwlmb3IgKGkg PSAwOyBpIDwgRFJQX1NZTl9SRUdfQ05UOyBpKyspIHsKPj4gKwkJc3luZF9yZWcgPSBEUlBfRUND X0RCX0VSUl9TWU4wICsgKGkgKiA0KTsKPj4gKwkJcmV0ID0gcmVnbWFwX3JlYWQoZHJ2LT5yZWdt YXAsIGRydi0+b2Zmc2V0c1tiYW5rXSArIHN5bmRfcmVnLAo+PiArCQkJCSAgJnN5bmRfdmFsKTsK Pj4gKwkJaWYgKHJldCkKPj4gKwkJCXJldHVybiByZXQ7Cj4+ICsJCWVkYWNfcHJpbnRrKEtFUk5f Q1JJVCwgRURBQ19MTENDLCAiRFJQX0VDQ19TWU4lZDogMHglOHhcbiIsIGksCj4+ICsJCQkgICAg c3luZF92YWwpOwo+PiArCX0KPj4gKwo+PiArCXJldCA9IHJlZ21hcF9yZWFkKGRydi0+cmVnbWFw LAo+PiArCQkJICBkcnYtPm9mZnNldHNbYmFua10gKyBEUlBfRUNDX0VSUk9SX1NUQVRVUzEsCj4+ ICsJCQkgICZkYl9lcnJfY250KTsKPj4gKwlpZiAocmV0KQo+PiArCQlyZXR1cm4gcmV0Owo+PiAr CWRiX2Vycl9jbnQgPSAoZGJfZXJyX2NudCAmIEVDQ19EQl9FUlJfQ09VTlRfTUFTSyk7Cj4+ICsJ ZWRhY19wcmludGsoS0VSTl9DUklULCBFREFDX0xMQ0MsICJEb3VibGUtQml0IGVycm9yIGNvdW50 OiAweCU0eFxuIiwKPj4gKwkJICAgIGRiX2Vycl9jbnQpOwo+PiArCj4+ICsJcmV0ID0gcmVnbWFw X3JlYWQoZHJ2LT5yZWdtYXAsCj4+ICsJCQkgIGRydi0+b2Zmc2V0c1tiYW5rXSArIERSUF9FQ0Nf RVJST1JfU1RBVFVTMCwKPj4gKwkJCSAgJmRiX2Vycl93YXlzKTsKPj4gKwlpZiAocmV0KQo+PiAr CQlyZXR1cm4gcmV0Owo+PiArCWRiX2Vycl93YXlzICY9IEVDQ19EQl9FUlJfV0FZU19NQVNLOwo+ PiArCWRiX2Vycl93YXlzID4+PSBFQ0NfREJfRVJSX1dBWVNfU0hJRlQ7Cj4+ICsJZWRhY19wcmlu dGsoS0VSTl9DUklULCBFREFDX0xMQ0MsICJEb3VibGUtQml0IGVycm9yIHdheXM6IDB4JTR4XG4i LAo+PiArCQkgICAgZGJfZXJyX3dheXMpOwo+PiArCj4+ICsJcmV0dXJuIHJldDsKPj4gK30KPj4g Kwo+PiArLyogRHVtcCBTeW5kcm9tZSByZWdpc3RlcnMgZm9yIERhdGEgUmFtIFNpbmdsZSBiaXQg ZXJyb3JzKi8KPj4gK3N0YXRpYyBpbnQgZHVtcF9kcnBfc2Jfc3luX3JlZyhzdHJ1Y3QgbGxjY19k cnZfZGF0YSAqZHJ2LCB1MzIgYmFuaykKPj4gK3sKPj4gKwlpbnQgc2JfZXJyX2NudCwgc2JfZXJy X3dheXMsIHJldCwgaTsKPj4gKwl1MzIgc3luZF9yZWcsIHN5bmRfdmFsOwo+PiArCj4+ICsJZm9y IChpID0gMDsgaSA8IERSUF9TWU5fUkVHX0NOVDsgaSsrKSB7Cj4+ICsJCXN5bmRfcmVnID0gRFJQ X0VDQ19TQl9FUlJfU1lOMCArIChpICogNCk7Cj4+ICsJCXJldCA9IHJlZ21hcF9yZWFkKGRydi0+ cmVnbWFwLCBkcnYtPm9mZnNldHNbYmFua10gKyBzeW5kX3JlZywKPj4gKwkJCQkgICZzeW5kX3Zh bCk7Cj4+ICsJCWlmIChyZXQpCj4+ICsJCQlyZXR1cm4gcmV0Owo+PiArCQllZGFjX3ByaW50ayhL RVJOX0NSSVQsIEVEQUNfTExDQywgIkRSUF9FQ0NfU1lOJWQ6IDB4JTh4XG4iLCBpLAo+PiArCQkJ ICAgIHN5bmRfdmFsKTsKPj4gKwl9Cj4+ICsKPj4gKwlyZXQgPSByZWdtYXBfcmVhZChkcnYtPnJl Z21hcCwKPj4gKwkJCSAgZHJ2LT5vZmZzZXRzW2JhbmtdICsgRFJQX0VDQ19FUlJPUl9TVEFUVVMx LAo+PiArCQkJICAmc2JfZXJyX2NudCk7Cj4+ICsJaWYgKHJldCkKPj4gKwkJcmV0dXJuIHJldDsK Pj4gKwlzYl9lcnJfY250ICY9IEVDQ19TQl9FUlJfQ09VTlRfTUFTSzsKPj4gKwlzYl9lcnJfY250 ID4+PSBFQ0NfU0JfRVJSX0NPVU5UX1NISUZUOwo+PiArCWVkYWNfcHJpbnRrKEtFUk5fQ1JJVCwg RURBQ19MTENDLCAiU2luZ2xlLUJpdCBlcnJvciBjb3VudDogMHglNHhcbiIsCj4+ICsJCSAgICBz Yl9lcnJfY250KTsKPj4gKwo+PiArCXJldCA9IHJlZ21hcF9yZWFkKGRydi0+cmVnbWFwLAo+PiAr CQkJICBkcnYtPm9mZnNldHNbYmFua10gKyBEUlBfRUNDX0VSUk9SX1NUQVRVUzAsCj4+ICsJCQkg ICZzYl9lcnJfd2F5cyk7Cj4+ICsJaWYgKHJldCkKPj4gKwkJcmV0dXJuIHJldDsKPj4gKwlzYl9l cnJfd2F5cyA9IHNiX2Vycl93YXlzICYgRUNDX1NCX0VSUl9XQVlTX01BU0s7Cj4+ICsKPj4gKwll ZGFjX3ByaW50ayhLRVJOX0NSSVQsIEVEQUNfTExDQywgIlNpbmdsZS1CaXQgZXJyb3Igd2F5czog MHglNHhcbiIsCj4+ICsJCSAgICBzYl9lcnJfd2F5cyk7Cj4+ICsKPj4gKwlyZXR1cm4gcmV0Owo+ PiArfQo+PiArCj4+ICtzdGF0aWMgaW50IGR1bXBfc3luX3JlZyhzdHJ1Y3QgZWRhY19kZXZpY2Vf Y3RsX2luZm8gKmVkZXZfY3RsLAo+PiArCQkJIGludCBlcnJfdHlwZSwgdTMyIGJhbmspCj4+ICt7 Cj4+ICsJc3RydWN0IGxsY2NfZHJ2X2RhdGEgKmRydiA9IGVkZXZfY3RsLT5wdnRfaW5mbzsKPj4g KwlpbnQgcmV0ID0gMDsKPj4gKwo+PiArCXN3aXRjaCAoZXJyX3R5cGUpIHsKPj4gKwljYXNlIExM Q0NfRFJBTV9DRToKPj4gKwkJcmV0ID0gZHVtcF9kcnBfc2Jfc3luX3JlZyhkcnYsIGJhbmspOwo+ PiArCQlicmVhazsKPj4gKwljYXNlIExMQ0NfRFJBTV9VRToKPj4gKwkJcmV0ID0gZHVtcF9kcnBf ZGJfc3luX3JlZyhkcnYsIGJhbmspOwo+PiArCQlicmVhazsKPj4gKwljYXNlIExMQ0NfVFJBTV9D RToKPj4gKwkJcmV0ID0gZHVtcF90cnBfc2Jfc3luX3JlZyhkcnYsIGJhbmspOwo+PiArCQlicmVh azsKPj4gKwljYXNlIExMQ0NfVFJBTV9VRToKPj4gKwkJcmV0ID0gZHVtcF90cnBfZGJfc3luX3Jl ZyhkcnYsIGJhbmspOwo+IAo+IFNvIHRob3NlIGZ1bmN0aW9ucyBsb29rIHZlcnkgc2ltaWxhciB0 byBvbmUgYW5vdGhlciBhbmQgdGh1cyBhcmUKPiBxdWFkcnVwbGVkIG9iamVjdCBjb2RlLiBZb3Ug Y291bGQgaGF2ZSBvbmUgZnVuY3Rpb24gaW5zdGVhZCBhbmQgcGFzcwo+IGluIHRoZSByZWdpc3Rl ciBhcyBhbiBhcmcuIE9yIHNvbWUgb3RoZXIgc21hcnRlciBzY2hlbWUgdG8gc2F2ZSBvYmplY3QK PiBzaXplLi4uCgpUaGVyZSBhcmUgYWN0dWFsbHkgNiBkaWZmZXJlbnQgcmVnaXN0ZXJzIGZvZSBl YWNoIGNhc2UgaGFuZGxlZCBpbiBlYWNoCmZ1bmN0aW9uLCB0aGF0J3Mgd2h5IHdlIGhhZCB0byBo YXZlIGRpZmZlcmVudCBmdW5jdGlvbnMgd2l0aCB0aGUgc2FtZQpvdXRsaW5lLiBJIGNhbiBleHBs b3JlIHRoZSB3YXkgb2YgaGF2aW5nIGEgc2luZ2xlIG1ldGhvZCBhbmQgY2F0ZWdvcml6ZSAKYmFz ZWQgb24KdGhlIGVycm9yIHR5cGUuIEJ1dCBJIGRvbid0IHRoaW5rIEkgd2lsbCBiZSByZWR1Y2lu ZyBhIGxvdCBvZiBvYmplY3QgCmNvZGUuIExldCBtZQpleHBsb3JlIG9uIHdoYXQgY2FuIEkgZG8g b24gdGhpcy4KCgo+IAo+PiArCQlicmVhazsKPj4gKwl9Cj4+ICsJaWYgKHJldCkKPj4gKwkJcmV0 dXJuIHJldDsKPj4gKwo+PiArCXJldCA9IHFjb21fbGxjY19jbGVhcl9lcnJvcnMoZXJyX3R5cGUs IGRydik7Cj4+ICsJaWYgKHJldCkKPj4gKwkJcmV0dXJuIHJldDsKPj4gKwo+PiArCWVycm9yc1tl cnJfdHlwZV0uZnVuYyhlZGV2X2N0bCwgMCwgYmFuaywgZXJyb3JzW2Vycl90eXBlXS5tc2cpOwo+ PiArCj4+ICsJcmV0dXJuIHJldDsKPj4gK30KPj4gKwo+PiArc3RhdGljIGlycXJldHVybl90Cj4+ ICtsbGNjX2VjY19pcnFfaGFuZGxlciAoaW50IGlycSwgdm9pZCAqZWRldl9jdGwpCj4gCj4gU3Ry YXkgIiAiIGFmdGVyIGZ1bmN0aW9uIG5hbWUuCkknbGwgY29ycmVjdCB0aGlzLgo+IAo+PiArewo+ PiArCXN0cnVjdCBlZGFjX2RldmljZV9jdGxfaW5mbyAqZWRhY19kZXZfY3RsOwo+PiArCWlycXJl dHVybl90IGlycV9yYyA9IElSUV9OT05FOwo+PiArCXUzMiBkcnBfZXJyb3IsIHRycF9lcnJvciwg aTsKPj4gKwlzdHJ1Y3QgbGxjY19kcnZfZGF0YSAqZHJ2Owo+PiArCWludCByZXQ7Cj4+ICsKPj4g KwllZGFjX2Rldl9jdGwgPSAoc3RydWN0IGVkYWNfZGV2aWNlX2N0bF9pbmZvICopZWRldl9jdGw7 Cj4+ICsJZHJ2ID0gZWRhY19kZXZfY3RsLT5wdnRfaW5mbzsKPj4gKwo+PiArCWZvciAoaSA9IDA7 IGkgPCBkcnYtPm51bV9iYW5rczsgaSsrKSB7Cj4+ICsJCS8qIExvb2sgZm9yIERhdGEgUkFNIGVy cm9ycyAqLwo+PiArCQlyZXQgPSByZWdtYXBfcmVhZChkcnYtPnJlZ21hcCwKPj4gKwkJCQkgIGRy di0+b2Zmc2V0c1tpXSArIERSUF9JTlRFUlJVUFRfU1RBVFVTLAo+PiArCQkJCSAgJmRycF9lcnJv cik7Cj4+ICsJCWlmIChyZXQpCj4+ICsJCQlyZXR1cm4gaXJxX3JjOwo+PiArCj4+ICsJCWlmIChk cnBfZXJyb3IgJiBTQl9FQ0NfRVJST1IpIHsKPj4gKwkJCWVkYWNfcHJpbnRrKEtFUk5fQ1JJVCwg RURBQ19MTENDLAo+PiArCQkJCSAgICAiU2luZ2xlIEJpdCBFcnJvciBkZXRlY3RlZCBpbiBEYXRh IFJhbVxuIik7Cj4+ICsJCQlkdW1wX3N5bl9yZWcoZWRldl9jdGwsIExMQ0NfRFJBTV9DRSwgaSk7 Cj4+ICsJCQlpcnFfcmMgPSBJUlFfSEFORExFRDsKPj4gKwkJfSBlbHNlIGlmIChkcnBfZXJyb3Ig JiBEQl9FQ0NfRVJST1IpIHsKPj4gKwkJCWVkYWNfcHJpbnRrKEtFUk5fQ1JJVCwgRURBQ19MTEND LAo+PiArCQkJCSAgICAiRG91YmxlIEJpdCBFcnJvciBkZXRlY3RlZCBpbiBEYXRhIFJhbVxuIik7 Cj4+ICsJCQlkdW1wX3N5bl9yZWcoZWRldl9jdGwsIExMQ0NfRFJBTV9VRSwgaSk7Cj4+ICsJCQlp cnFfcmMgPSBJUlFfSEFORExFRDsKPj4gKwkJfQo+PiArCj4+ICsJCS8qIExvb2sgZm9yIFRhZyBS QU0gZXJyb3JzICovCj4+ICsJCXJldCA9IHJlZ21hcF9yZWFkKGRydi0+cmVnbWFwLAo+PiArCQkJ CSAgZHJ2LT5vZmZzZXRzW2ldICsgVFJQX0lOVEVSUlVQVF8wX1NUQVRVUywKPj4gKwkJCQkgICZ0 cnBfZXJyb3IpOwo+PiArCQlpZiAocmV0KQo+PiArCQkJcmV0dXJuIGlycV9yYzsKPj4gKwkJaWYg KHRycF9lcnJvciAmIFNCX0VDQ19FUlJPUikgewo+PiArCQkJZWRhY19wcmludGsoS0VSTl9DUklU LCBFREFDX0xMQ0MsCj4+ICsJCQkJICAgICJTaW5nbGUgQml0IEVycm9yIGRldGVjdGVkIGluIFRh ZyBSYW1cbiIpOwo+PiArCQkJZHVtcF9zeW5fcmVnKGVkZXZfY3RsLCBMTENDX1RSQU1fQ0UsIGkp Owo+PiArCQkJaXJxX3JjID0gSVJRX0hBTkRMRUQ7Cj4+ICsJCX0gZWxzZSBpZiAodHJwX2Vycm9y ICYgREJfRUNDX0VSUk9SKSB7Cj4+ICsJCQllZGFjX3ByaW50ayhLRVJOX0NSSVQsIEVEQUNfTExD QywKPj4gKwkJCQkgICAgIkRvdWJsZSBCaXQgRXJyb3IgZGV0ZWN0ZWQgaW4gVGFnIFJhbVxuIik7 Cj4+ICsJCQlkdW1wX3N5bl9yZWcoZWRldl9jdGwsIExMQ0NfVFJBTV9VRSwgaSk7Cj4+ICsJCQlp cnFfcmMgPSBJUlFfSEFORExFRDsKPj4gKwkJfQo+PiArCX0KPj4gKwo+PiArCXJldHVybiBpcnFf cmM7Cj4+ICt9Cj4+ICsKPj4gK3N0YXRpYyBpbnQgcWNvbV9sbGNjX2VkYWNfcHJvYmUoc3RydWN0 IHBsYXRmb3JtX2RldmljZSAqcGRldikKPj4gK3sKPj4gKwlzdHJ1Y3QgbGxjY19kcnZfZGF0YSAq bGxjY19kcml2X2RhdGEgPSBwZGV2LT5kZXYucGxhdGZvcm1fZGF0YTsKPj4gKwlzdHJ1Y3QgZWRh Y19kZXZpY2VfY3RsX2luZm8gKmVkZXZfY3RsOwo+PiArCXN0cnVjdCBkZXZpY2UgKmRldiA9ICZw ZGV2LT5kZXY7Cj4+ICsJdTMyIGVjY19pcnE7Cj4+ICsJaW50IHJjOwo+PiArCj4+ICsJcmMgPSBx Y29tX2xsY2NfY29yZV9zZXR1cChsbGNjX2RyaXZfZGF0YS0+YmNhc3RfcmVnbWFwKTsKPj4gKwlp ZiAocmMpCj4+ICsJCXJldHVybiByYzsKPj4gKwo+PiArCS8qIEFsbG9jYXRlIGVkYWMgY29udHJv bCBpbmZvICovCj4+ICsJZWRldl9jdGwgPSBlZGFjX2RldmljZV9hbGxvY19jdGxfaW5mbygwLCAi cWNvbS1sbGNjIiwgMSwgImJhbmsiLAo+PiArCQkJCQkgICAgICBsbGNjX2RyaXZfZGF0YS0+bnVt X2JhbmtzLCAxLAo+PiArCQkJCQkgICAgICBOVUxMLCAwLAo+PiArCQkJCQkgICAgICBlZGFjX2Rl dmljZV9hbGxvY19pbmRleCgpKTsKPj4gKwo+PiArCWlmICghZWRldl9jdGwpCj4+ICsJCXJldHVy biAtRU5PTUVNOwo+PiArCj4+ICsJZWRldl9jdGwtPmRldiA9IGRldjsKPj4gKwllZGV2X2N0bC0+ bW9kX25hbWUgPSBkZXZfbmFtZShkZXYpOwo+PiArCWVkZXZfY3RsLT5kZXZfbmFtZSA9IGRldl9u YW1lKGRldik7Cj4+ICsJZWRldl9jdGwtPmN0bF9uYW1lID0gImxsY2MiOwo+PiArCWVkZXZfY3Rs LT5wYW5pY19vbl91ZSA9IExMQ0NfRVJQX1BBTklDX09OX1VFOwo+PiArCj4+ICsJZWRldl9jdGwt PnB2dF9pbmZvID0gKHN0cnVjdCBsbGNjX2Rydl9kYXRhICopIGxsY2NfZHJpdl9kYXRhOwo+IAo+ IFdoeSBpcyB0aGF0IGNhc3QgbmVlZGVkPwpOb3QgbmVlZGVkLCByZWR1bmRhbnQsIHRoZSB2YXJp YWJsZSBpcyBhbHJlYWR5IG9mIHRoYXQgdHlwZS4gSSdsbCBjaGVjayAKaWYgdGhlIGNhc3QgaXMg bmVlZGVkIGluIHRoZSBmaXJzdCBsaW5lIG9mIHRoaXMgZnVuY3Rpb24uCg==